DJLXT384LE Intel, DJLXT384LE Datasheet - Page 38

• Manufacturer Part Number: DJLXT384LE
• Manufacturer: Intel

Specifications of DJLXT384LE

• Lead Free Status / RoHS Status: Not Compliant

Intel
38
Table 11. Clocks and Clock-Related Signals (Sheet 2 of 2)
®
LXT384 Octal T1/E1/J1 S/H PCM Transceiver with JA
MCLK
RCLK
SCLK
TCLK
1. DI: Digital Input
Signal
Name
QFP
Pin
10
PBGA
Ball
E1
Signal
Type
DI
Master Clock Input.
MCLK is an independent, free-running reference clock that must be
used at 1.544 MHz for T1 operation or 2.048 MHz for E1 operation, to
generate the following internal reference signals:
If MCLK is:
NOTE:
Caution: Whenever MCLK is not provided, the LXT384 Transceiver is
Receive Clock Output 7:0.
For information on RCLK, see
Shift Clock Input.
For information on SCLK, see
Bus and Interface
Transmit Clock Input 7:0.
For information on TCLK, see
• Reference clock during a blue-alarm transmit-all-ones condition.
• Generation of RCLK signal during a loss-of-signal condition.
• Timing reference for the integrated clock-recovery unit, and the
• Wait-state generation logic for host processors that use parallel
• Low continuously, the complete receive path is powered down and
• High continuously, the phase-locked loop clock-recovery circuit is
• MCLK is not required if the LXT384 Transceiver is used as an
• The TAOS generator uses MCLK as a timing reference. To ensure
• If MCLK is not provided, the LXT384 Transceiver cannot be used
integrated digital jitter attenuator.
interfaces.
output pins RCLK, RPOS, and RNEG are switched to a high-
impedance tristate.
disabled and the LXT384 Transceiver operates as only a simple
data receiver (without clock recovery).
analog front end without clock recovery and jitter attenuation.
the output frequency is within specification limits, MCLK must
have the applicable stability.
for data recovery with Motorola processors because wait states
cannot be added. (Wait-state generation through ACK is not
available.)
forced into a static state, possibly causing the TTIP/TRING
outputs to overheat. To prevent overheating, see
6.5, “Line-Interface
Signals”.
Signal Description
Protection”.
Section 5.3, “Framer/Mapper
Section 5.2, “Microprocessor-Standard
Section 5.3, “Framer/Mapper
Revision Date: November 28, 2005
Document Number: 248994
Revision Number: 005
Section
Signals”.
Signals”.