STLC5466 STMicroelectronics, STLC5466 Datasheet - Page 72

• Manufacturer Part Number: STLC5466
• Description: RF Wireless Misc Multi-HDLC Sw Matrix
• Manufacturer: STMicroelectronics
• Type: Telecom ICr

Specifications of STLC5466

• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: LQFP-176
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

STLC5466
VII.2 - Receive Descriptor
This receive descriptor is located in shared memory. The quantity of descriptors is limited by the memory
size only.
The 5 first words located in shared memory to RDA+00 from RDA+08 are written by the microprocessor
and read by the DMAC only. The 6th word located in shared memory in RDA+10 is written by the DMAC
only during the frame reception and read by the microprocessor.
SOB
RBA
RDA
NRDA : Next Receive Descriptor Address. LSB of NRDA Low is at Zero mandatory.
NBR
VII.2.1 - Bits written by the Microprocessor only
IBC
EOQ : End Of Queue.
SIM
VII.2.2 - Bits written by the Rx DMAC only
72/130
RDA+00
RDA+02
RDA+04
RDA+06
RDA+08
RDA+10
FR
1
1
0
0
: Size Of the Buffer associated to descriptor. These 12bits allows to reach 4096 bytes).
: Receive Buffer Address. LSB of RBA Low is at Zero mandatory.
: Receive Descriptor Address.
: Number of Bytes Received (up to 4096).
: Interrupt if the buffer has been completed.
:
If SOB = 0, DMAC goes to next descriptor.
IBC=1, the DMAC generates an interrupt if the buffer has been completed.
EOQ=1, the DMAC stops immediately its reception generates an interrupt (HDLC = 1 in IR) and
waits a command from the HRCR (HDLC Receive Command Register).
EOQ=0, the DMAC continues.
SIM=1, when an event occurs the RX DMAC thanks to Interrupt controller stores the features of
this event in the HDLC Interrupt Queue but the Interrupt Register is not written. So there is no
interrupt signal on INT0 pin.
SIM=0, when an event occurs the RX DMAC thanks to Interrupt controller stores the features of
this event in the Interrupt Queue and the HDLC bit of the Interrupt Register is put at “1”. So INT0
pin goes to Vcc if HDLC bit is not masked.
ABT
Signal Interrupt Mask
0
0
0
0
FR
15
OVF
0
0
0
0
ABT
SIM
14
FCRC
0
1
0
0
OVF
IBC
13
The frame has been received without error. The end of frame is in this buffer.
The frame has been received with false CRC.
If NBR is different to 0, the buffer related to this descriptor is completed.The end
of frame is not in this buffer.
If NBR is equal to 0, the Rx DMAC is receiving a frame.
Not used
Not used
EOQ
FCR
12
C
Next Receive Descriptor Address Low (16 bits)
Receive Buffer Address Low (16 bits)
11
10
9
Number of Bytes Received (NBR)
8
Size Of the Buffer (SOB)
Definition
7
6
5
NRDA High (8 bits)
RBA High (8 bits)
4
3
2
1
0
0