STLC5466 STMicroelectronics, STLC5466 Datasheet - Page 48

• Manufacturer Part Number: STLC5466
• Description: RF Wireless Misc Multi-HDLC Sw Matrix
• Manufacturer: STMicroelectronics
• Type: Telecom ICr

Specifications of STLC5466

• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: LQFP-176
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

STLC5466
VI.14 - HDLC Receive Command Register 1
READ : READ COMMAND MEMORY
CH0/4 : These five bits define one of 32 channels.
C1/C0 : COMMAND BITS
C1/C0 : STATUS BITS
P0/1
48/130
bit15
CH4
CH3
: PROTOCOL BITS
READ = 1, READ COMMAND MEMORY.
READ = 0, WRITE COMMAND MEMORY.
C1
C1
P1
0
0
1
1
0
0
1
1
0
0
1
1
CH2
C0
C0
P0
0
1
0
1
0
1
0
1
0
1
0
1
CH1
ABORT; if this command occurs during receiving a current frame, HDLC Controller stops the
reception, generates an interrupt and waits new command such as START or CONTINUE.
If this command occurs after receiving a frame, HDLC Controller generates an interrupt and
waits a new command such as START or CONTINUE.
START; Rx DMA Controller is now going to transfer first frame into buffer related to the initial
descriptor. The initial descriptor address is provided by the Initiate Block located in external
memory.
CONTINUE; Rx DMA Controller is now going to transfer next frame into buffer related to next
descriptor. The next descriptor address is provided by the previous descriptor from which the
related frame had been already received.
HALT; after receiving a frame, HDLC Controller stops the reception, generates an interrupt
and waits a new command such as START or CONTINUE.
ABORT; the received current frame has been aborted (seven “1” at least have been received)
or the microprocessor has written ABORT.
The HDLC Controller waits a new command such as START or CONTINUE
START; the microprocessor has written START.The HDLC Controller has not taken into ac-
count the command yet.
CONTINUE; RX DMA Controller is transferring frames
HALT; HDLC Controller stops the reception, generates an interrupt and waits a new com-
mand such as START or CONTINUE.
HDLC
Transparent Mode 1 (one byte per timeslot); the fill character defined in FCR Register is taken
into account.
Transparent Mode 2 (one byte per timeslot); the fill character defined in FCR Register is not
taken into account.
Reserved
CH0 READ AR21 AR20 AR11 AR10 CRC
Command Bits written by the microprocessor
Status Bits read by the microprocessor
After reset (0000)
bit8
Transmission Mode
bit7
H
FM
P1
P0
HRCR1 (1A)
C1
bit0
C0
H