STLC5466 STMicroelectronics, STLC5466 Datasheet - Page 23

• Manufacturer Part Number: STLC5466
• Description: RF Wireless Misc Multi-HDLC Sw Matrix
• Manufacturer: STMicroelectronics
• Type: Telecom ICr

Specifications of STLC5466

• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: LQFP-176
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

III.6.2.2 - Read Fetch Memory
When the microprocessor delivers the address
word named An to read data named [An] out of the
shared memory in fact it reads data [An] from the
Read Fetch Memory (64 words).
The number of wait cycle for the microprocessor is
strongly reduced. If An, address word delivered by
the microprocessor, and data [An] are already in
the Read Fetch Memory and validated then there
is no wait time for the microprocessor.
The source of [An] is truly the shared memory
whatever An.
Data [An] if validated in Fetch Memory and Data
[An] in shared memory are always the same.
III.6.2.3 - Definition of the Interface for the dif-
ferent microprocessors
The signals connected to the microprocessor in-
terface are presented on the following figures for
the different microprocessor (see Figures).
III.7 - Memory Interface
III.7.1 - Function Description
The memory interface allows the connection of
Synchronous Dynamic RAM. The memory inter-
face will address up to 16 Megabytes. The memo-
ry location is always organized in 16 bits.
The memory is shared between the Multi-HDLC
and the microprocessor. The access to the mem-
ory is arbitrated by an internal function of the cir-
cuit: the bus arbitration.
III.7.2 - Choice of memory versus microproces-
sor and capacity required
The memory interface depends on the memory
chips which are connected. The memory chips will
be chosen versus their organization.
Example1: if the application requires 8 or 16 bit
size, one capability is offered:
– 1 SDRAM Circuit (1Mx16).
Example2: if the application requires 16 bit Proc-
essor and 4 Megaword Shared memory size,
three capabilities are offered:
– 4 SDRAM Circuits (1Mx16) or
– 4 SDRAM Circuits (4Mx4) or
– 1 SDRAM Circuit (4Mx16).
.Example3: if the application requires 8 Megaword
Shared memory size three capabilities are offered:
– 8 SDRAM Circuits (4Mx4) or
– 2 SDRAM Circuits (4Mx16) or
– 2 SDRAM Circuit (8Mx8).
Processor and 1 Megaword Shared memory
III.7.3 - Memory Cycle
Some parameters are frozen:
– Burst Read and Single Write.
– The Burst Length is 4.
– The burst data is addressed in sequential mode.
The programmable parameters are:
– Latency Mode
– selected circuit organisation
– the
III.7.4 - Memories composed of different cir-
cuits
III.7.4.1 - Memory obtained with 1M x16 SDRAM
circuit
The Address bits delivered by the Multi-HDLC for
1M x 16 SDRAM circuits are:
– ADM11 for Bank select corresponding with A20
– ADM0/10 for Row address inputs corresponding
– ADM0/7 for Column address inputs correspond-
III.7.4.2 - Memory obtained with 2M x 8 SDRAM
circuit
The Address bits delivered by the Multi-HDLC for
2M x 8 SDRAM circuits are:
– ADM11 for Bank select corresponding with A21
– ADM0/10 for Row address inputs corresponding
– ADM0/8 for Column address inputs correspond-
SDRAM are at the Master Clock frequency
(33MHz, 50MHz, 66MHz)
delivered by the microprocessor
with A9/19 delivered by the microprocessor
ing with A1/8 delivered by the microprocessor
delivered by the microprocessor
with A10/20 delivered by the microprocessor
ing with A1/9 delivered by the microprocessor
Signals
NCE3
NCE2
NCE1
NCE0
Signals
UDQM
LDQM
exchanges
A22
A0 or equivalent
1
1
0
0
A21
between
1
0
1
0
1
0
Signals
UDQM
LDQM
Multi-HDLC
NLDS
0
1
STLC5466
or equiva-
NUDS
lent
23/130
1
0
A0
1
0
and