STLC5466 STMicroelectronics, STLC5466 Datasheet - Page 33

• Manufacturer Part Number: STLC5466
• Description: RF Wireless Misc Multi-HDLC Sw Matrix
• Manufacturer: STMicroelectronics
• Type: Telecom ICr

Specifications of STLC5466

• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: LQFP-176
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

VI.3 - Input Multiplex Configuration Register 0
See definition in next Paragraph.
AFAB : Advanced Frame A/B Signal
MBL
SBV
bit15
LP3 DEL3 ST(3)1 ST(3)0 LP2 DEL2 ST(2)1 ST(2)0 LP1 DEL1 ST(1)1 ST(1)0 LP0 DEL0 ST(0)1 ST(0)0
: Memory Bus Low impedance
: Six Bit Validation (A, E, S1/S4 bits). Global validation for 16 channels (Upstream and down-
AFAB = 1, the advance of FRAMEA Signal and FRAMEB Signal is 0.5 bit time versus the signal
FRAMEA (or B).
AFAB = 0, FRAMEA Signal and FRAMEB Signal are in accordance with the clock timing.
MBL = 1, the shared memory bus is at low impedance between two memory cycles and also at
low impedance during a memory cycle.
The memory bus includes Control bus, Address bus except Data bus. One Multi-HDLC can be
connected to the shared memory. 16 pull-up resistors must be connected on the data bus.
MBL = 0, the shared memory bus is at high impedance between two memory cycles and at
low impedance during a write memory cycle.
Several Multi-HDLC s can be connected to the shared memory. One pull-up resistor is recom-
mended on each wire (Control bus, Address bus, Data bus).
stream).
SBV=1, in reception, the six bit word (A, E, S1/S4) located in the same timeslot as D channel
can be received from any input timeslot; when this word is received identical twice consecutive-
ly, it is stored in the external shared memory and an interrupt is generated if not masked (like
the reception of primitive from C/I channel).
Sixteen independent detections are performed if the contents of any input timeslot is switched
in the timeslot 4n+3 of two GCI multiplexes (corresponding to DOUT4 and DOUT5) with (0
In transmission a six bit word (A, E, S1/S4) can be transmitted continuously to any output times-
lot via the TCIR. This word (A, E, S1/S4) is set instead of primitive (C1, C2, C3, C4) and A, E
bits received from the timeslot 4n+3 of two GCI multiplexes and the new contents of this timeslot
4n+3 must be switched on the selected output timeslot.
SBV=0, the 16 six bit detections are not validated.
.
7). Only the contents of D channel will be transmitted from input timeslot to GCI multiplexes.
MBL
1
0
A, C
A, C
Bus
D
D
During the whole of cycle duration
Write cycle
After reset (0000)
L
L
L
L
bit8
bit7
H
Read cycle
L
Z
L
Z
On the outside of cycle
L
Z
Z
Z
IMCR0 (04)
STLC5466
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bit0
H
n