STLC5466 STMicroelectronics, STLC5466 Datasheet - Page 34

• Manufacturer Part Number: STLC5466
• Description: RF Wireless Misc Multi-HDLC Sw Matrix
• Manufacturer: STMicroelectronics
• Type: Telecom ICr

Specifications of STLC5466

• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: LQFP-176
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

STLC5466
VI.4 - Input Multiplex Configuration Register 1
ST(i)0 : STEP0 for each Input Multiplex(i) with (0
ST(i)1 : STEP1 for each Input Multiplex(i) with (0
DEL(i) : DELAYED Multiplex i(0
LP (i) : LOOPBACK 0/7
N.B. If DIN4 and DIN5 are GCI Multiplexes: then ST(4)1 = ST(4)0 = 0 and ST(5)1 = ST(5)0 = 0 normally.
VI.5 - Output Multiplex Configuration Register 0
See definition in next Paragraph.
VI.6 - Output Multiplex Configuration Register 1
ST(i)0 : STEP0 for each Output Multiplex(i) with (0
ST(i)1 : STEP1 for each Output Multiplex(i) with (0
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OMV3 DEL3 ST(3)1 ST(3)0 OMV2 DEL2 ST(2)1 ST(2)0 OMV1 DEL1 ST(1)1 ST(1)0 OMV0 DEL0 ST(0)1 ST(0)0
OMV7 DEL7 ST(7)1 ST(7)0 OMV6 DEL6 ST(6)1 ST(6)0 OMV5 DEL5 ST(5)1 ST(5)0 OMV4 DEL4 ST(4)1 ST(4)0
bit15
LP7 DEL7 ST(7)1 ST(7)0 LP6 DEL6 ST(6)1 ST(6)0 LP5 DEL5 ST(5)1 ST(5)0 LP4 DEL4 ST(4)1 ST(4)0
bit15
bit15
.
When IMTD = 0 (bit of SMCR), DEL = 1 is not taken into account by the circuit.
If TDM is at 2048 kb/s,1/2 bit-time is 244 ns,
If TDM is at 4096 kb/s,1/2 bit-time is 122 ns.
LPi = 1, Output Multiplex(i) is put instead of Input Multiplex(i) with (0 i 7). LOOPBACK is trans-
parent or not in accordance with OMVi (bit of Output Multiplex Configuration Register).
LPi = 0, Normal case, Input Multiplex(i) with (0
DEL (i)
X
1
1
1
0
0
0
ST (i) 1
0
0
1
1
0
1
1
ST (i) 0
0
1
0
1
1
0
1
i
7).
Each received bit is sampled at 3/4 bit-time without delay (TDM at 2
Mb/s).First bit of the frame is defined by Frame synchronization Signal.
Each received bit is sampled with 1/2 bit-time delay
Each received bit is sampled with 1 bit-time delay
Each received bit is sampled with 2 bit-time delay
Each received bit is sampled with 1/2 bit-time advance
Each received bit is sampled with 1 bit-time advance
Each received bit is sampled with 2 bit-time advance
After reset (0000)
After reset (0000)
After reset (0000)
bit8
bit8
bit8
STEP for each Input Multiplex 0/7 delayed or not
i
i
bit7
bit7
bit7
i
i
7), delayed or not.
7), delayed or not.
7), delayed or not.
7), delayed or not.
i
H
H
H
7) is taken into account.
OMCR1 (0A)
OMCR0 (08)
IMCR1 (06)
bit0
bit0
bit0
H
H
H