STLC5466 STMicroelectronics, STLC5466 Datasheet - Page 59

• Manufacturer Part Number: STLC5466
• Description: RF Wireless Misc Multi-HDLC Sw Matrix
• Manufacturer: STMicroelectronics
• Type: Telecom ICr

Specifications of STLC5466

• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: LQFP-176
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

VI.31 - Timer Register 1
This programmable register indicates the time at the end of which the Watch Dog delivers logic “1” on the
pin WDO (which is an output) but only if the microprocessor does not reset the counter assigned (with the
help of WDR bit of IDCR (Identification and Dynamic Command Register) during the time defined by the
Timer Register.When the microprocessor does not reset the counter, the pin WDO delivers logic “1 as
soon as delta T plus programmed time are reached. (delta T from one to two clock periods of the associ-
ated counter).
Remark:
the time indicated in this register is obtained when the clock period of the associated counter is 250 mi-
croseconds. The minimum programmable time is four clock periods (1 millisecond in this case); the dura-
tion of the pulse delivered by the pin WDO is one clock period (250 microseconds).
The Timer Register and its counter can be used as a time base by the microprocessor. An interrupt (TIM)
is generated at each period defined by the Timer Register if the microprocessor does not reset the counter.
To reset the counter, WDR (bit of IDCR) must be set to “1” by the microprocessor.
The Watch Dog or the Timer is incremented by the Frame Synchronisation clock divided by two (TBFS=1)
or by a submultiple of MCLK signal (TBFS=0; TBFS, bit of Interrupt Queue Size Register).
Example:
TBFS=1 if the Frame Synchronisation clock is at 8 kHz, the period of the counter clock is 250 microsec-
onds
TBFS=0 if MCLK clock is at 32768 kHz the clock period of the counter is 250 microseconds (inverse of
32768kHz divided by 8192).
When TSV=1{bit of General Configuration Register)} this programmable register (TIMR1) is not signifi-
cant.
VI.32 - Test Register
T15/0 : Test bits 0/15
bit15
bit15
S3
r
S2
e
These bits are reserved for the test of the circuit in production.The use of these bits is forbidden.
0 to 5s
S1
s
S0
e
MS9
r
MS8
v
MS7
e
After reset (0800)
MS6
bit8
bit8
d
MS5
0 to 999ms
bit7
bit7
r
H
MS4
e
MS3
s
MS2
e
MS1
r
MS0
v
TIMR1 (3C)
0 to 3x0.25ms
STLC5466
MM1
e
TR (3E)
59/130
MM0
bit0
bit0
d
H
H