STLC5466 STMicroelectronics, STLC5466 Datasheet - Page 16

• Manufacturer Part Number: STLC5466
• Description: RF Wireless Misc Multi-HDLC Sw Matrix
• Manufacturer: STMicroelectronics
• Type: Telecom ICr

Specifications of STLC5466

• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: LQFP-176
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

STLC5466
Kbit/s then TDM2 or/and TDM3 are not available
externally they are used internally to perform the
function.
See figure: Upstream switching at 32 kb/s.
III.1.8 - Switching at 16 Kbit/s
The TDM4 and TDM5 can be GCI multiplexes.
Each GCI multiplex comprises 8 GCI channels.
Each GCI channel comprises one D channel at 16
Kbit/s. See figure: GCI channel definition, GCI
Synchro signal delivered by the Multi-HDLC
It is possible to switch the contents of 16 D chan-
nels from the 16 GCI channels to 4 timeslots of the
256 output timeslots.
In the other direction the contents of an selected
timeslot is automatically switched to 4 D channels
at 16 Kbit/s.
See Connection Memory Data Register CMDR
(0E)H.
III.2 - HDLC CONTROLLER
III.2.1 - Function description
Two independent HDLC controllers allow to proc-
ess 64 channels.
Each internal HDLC controller can run up to 32
channels in a conventional HDLC mode or in a
transparent (non-HDLC) mode (configurable per
channel).
Each channel bit rate is programmable from 4kbit/
s to 64kbit/s. All the configurations are also possi-
ble from 32 channels (from 4 to 64 kbit/s) to one
channel at 2 Mbit/s.
– First HDLC controller
In reception for the first HDLC controller, the con-
tents of each time slot can directly come from the
input TDM DIN8 (direct HDLC Input) or from any
other TDM input after switching towards the output
7 of the matrix (configurable per time slot).
In transmission, the HDLC frames are sent on the
output DOUT6 and on the output CB1 (with or
without contention mechanism), or are switched
towards the other TDM output via the input 7 of the
matrix.
– Second HDLC controller
In reception for the second HDLC controller, the
contents of each time slot can directly come from
the input TDM DIN9 (direct HDLC Input) or from
any other TDM input after switching towards the
output 6 of the matrix (configurable per time slot).
In transmission, the HDLC frames are sent on the
output DOUT7 and on the output CB2 (with or
without contention mechanism), or are switched
16/130
See figure: Downstream switching at 32 kb/s.
towards the other TDM output via the input 6 of the
matrix.
III.2.1.1 - Format of the HDLC Frame
The format of an HDLC frame is the same in re-
ceive and transmit direction and shown here after.
III.2.1.2 - Composition of an HDLC Frame
– Opening Flag
– One or two bytes for address recognition (recep-
– Data bytes with bit stuffing
– Frame Check Sequence: CRC with polynomial
– Closing Flag.
III.2.1.3 - Description and Functions of the
HDLC Bytes
– FLAG
– ABORT
tion) and insertion (transmission)
G(x) = x
The binary sequence 01111110 marks the be-
ginning and the end of the HDLC Frame.
Note: In reception, three possible flag configura-
tion are allowed and correctly detected:
- two normal consecutive flags:
...01111110 01111110...
- two consecutive flags with a “0” common:
...011111101111110...
- a global common flag:...01111110...
this flag is the closing flag for the current frame
and the opening flag for the next frame
The binary sequence 1111111 marks an Abort
command.
In reception, seven consecutive 1’s, inside a
message, are detected as an abort command
and generates an interrupt to the host.
In transmit direction, an abort is sent upon com-
mand of the micro-processor. No ending flag is
expected after the abort command.
16
Command Field (second byte)
Address Field (second byte)
+x
Command Field (first byte)
Address Field (first byte)
12
FCS (second byte)
+x
Data (first byte)
Data (last byte)
FCS (first byte)
Data (optional)
Opening Flag
Closing Flag
5
+1