STLC5466 STMicroelectronics, STLC5466 Datasheet - Page 32

• Manufacturer Part Number: STLC5466
• Description: RF Wireless Misc Multi-HDLC Sw Matrix
• Manufacturer: STMicroelectronics
• Type: Telecom ICr

Specifications of STLC5466

• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: LQFP-176
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

STLC5466
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TSV
EVM
D7
SYN0/1 : SYNCHRONIZATION
HCL
CSD
SELB : SELECT B
BSEL : B SELECTED (this bit is read only)
SCL
: Time Stamping Validated
: EXTERNAL VCXO MODE
: First HDLC controller connected to MATRIX
: HIGH BIT CLOCK
: Clock Supervision Deactivation
: Single Clock
TSV = 1, the time stamping counter becomes a free binary counter and counts down from
65535 to 0 in step of 250 microseconds (Total = 16384ms). So if an event occurs when the
counter indicates A and if the next event occurs when the counter indicates B then:
t = (A-B) x 250 microseconds is the time which has passed between the two events which have
been stored in memory by the Interrupt Controller (for Rx C/I and Rx MON CHANNEL only).
TSV = 0, the counter becomes a decimal counter.The Timer Register and this decimal counter
constitute a Watch Dog or a Timer.
EVM=1,VCXO Synchronization Counter is divided by 32.
EVM=0,VCXO Synchronization Counter is divided by 30.
D7 = 1, the first transmit HDLC controller is connected to matrix input 7, the DIN7 signal is ig-
nored.
D7 = 0, the DIN7 signal is taken into account by the matrix, the first transmit HDLC controller is
ignored by the matrix.
SYN0/1: these two bits define the signal applied on FRAMEA/B inputs.
This bit defines the signal applied on CLOCKA/B inputs.
HCL = 1, bit clock signal is at 8192kHz (or 6144kHz)
HCL= 0, bit clock signal is at 4096kHz (or 3072kHz)
CSD = 1, the lack of selected clock is not seen by the microprocessor; INT1 is masked.
CSD = 0, when the selected clock disappears the INT1 pin goes to 5V, 250ms after this
disappearance.
SELB = 1, FRAME B and CLOCK B must be selected.
SELB = 0, FRAME A and CLOCK A must be selected.
BSEL = 1, FRAME B and CLOCK B are selected.
BSEL = 0, FRAME A and CLOCK A are selected.
This bit defines the signal delivered by DCLK output pin.
CLOCKA/B inputs at 4096kHz or 8192kHz
SCL = 1, Data Clock is at 2048kHz.
SCL = 0, Data Clock is at 4096kHz.
CLOCKA/B inputs at 3072kHz or 6144kHz
SCL = 1, Data Clock is at 1536kHz.
SCL = 0, Data Clock is at 3072kHz.
SYN1
0
0
1
1
SYN0
0
1
0
1
SY Interface
GCI Interface (the signal defines the first bit of the frame)
Vstar Interface (the signal defines third bit of the frame)
Not used
Signal applied on FRAMEA/B inputs