STLC5466 STMicroelectronics, STLC5466 Datasheet - Page 37

• Manufacturer Part Number: STLC5466
• Description: RF Wireless Misc Multi-HDLC Sw Matrix
• Manufacturer: STMicroelectronics
• Type: Telecom ICr

Specifications of STLC5466

• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: LQFP-176
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

M1/0
SW0
SW1
VI.8 - Connection Memory Data Register
This 16 bit register is constituted by two 8 bit registers:
SOURCE REGISTER (SRCR) and CONTROL REGISTER (CTLR).
SOURCE REGISTER (SRCR)
This register defines the source when this source is located on an Input Time Division Multiplex ITDMp:
ITS 0/4 : Input time slot 0/4 define ITSx with: 0
IM0/2
When D channels are multiplexed, see S0/S1 definition and tables here after.
bit15
SCR
: Input Time Division Multiplex 0/2 define ITDMp with: 0
PS
: Data Rate of TDM0/8;
: Switching at 32 Kbit/s for the TDM0 (DIN0/DOUT0)
: Switching at 32 Kbit/s for the TDM1 (DIN1/DOUT1)
These two bits indicate the data rate of height Time Division Multiplexes TDM0/7 relative to
DIN0/7 and DOUT0/7. The table below shows the different data rates with the clock frequency
defined by HCL bit (General Configuration Register).
N.B. The data rate of the Time Division Multiplex relative to DIN8, CB and Echo pins are at
2048 Kbit/s or1536 Kbit/s depending on M1/0 only.
SW0=1, DIN0 can receive 64 channels at 32 Kbit/s.
DIN2/DOUT2 are not available.
DIN2 is used to receive internally TDM0 (DIN0) after 4 bit shifting
DOUT2 is used to multiplex internally TDM2 and TDM4.
SW0=0, DIN0 receives 32 (or 24) channels at 64 Kbit/s or 64 channels at 64 Kbit/s depending
on DR04 bit and ClockA/B.
SW1=1, DIN1 can receive 64 channels at 32 Kbit/s.
DIN3/DOUT3 are not available.
DIN3 is used to receive internally TDM1(DIN1) after 4 bit shifting
DOUT3 is used to multiplex internally TDM3 and TDM5.
SW1=0, DIN1 receives 32 (or 24) channels at 64 Kbit/s or 64 channels at 64 Kbit/s depending
on DR04 bit and ClockA/B.
CONTROL REGISTER (CTLR)
M1 M0
PRSA
0
0
1
1
0
1
0
1
S1
2048 (or 4096 in accordance with DR0x4)
1536 (or 3072 in accordance with DR0x4)
S0
Data Rate of TDM0/7 in Kbit/s
OTSV LOOP
Reserved
Reserved
After reset (0000)
bit8
SI
x
31;
IM2
bit7
H
IM1
SOURCE REGISTER (SRCR)
p
IM0
7.
ITS 4 ITS 3 ITS 2 ITS 1 ITS 0
CLOCKA/B signal frequency
4096 KHz
3072 KHz
HCL=0
8192 KHz
6144KHz
CMDR (0E)
STLC5466
HCL=1
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bit0
H