STLC5466 STMicroelectronics, STLC5466 Datasheet - Page 52

• Manufacturer Part Number: STLC5466
• Description: RF Wireless Misc Multi-HDLC Sw Matrix
• Manufacturer: STMicroelectronics
• Type: Telecom ICr

Specifications of STLC5466

• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: LQFP-176
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

STLC5466
VI.20 - GCI Channels Definition Register 2
For definition see GCI Channels Definition Register above.
VI.21 - GCI Channels Definition Register 3
For definition see GCI Channels Definition Register above.
VI.22 - Transmit Command / Indicate Register
When this register is written by the microprocessor, these different bits mean:
C6/1
A, E,
S1 to S4
52/130
READ
CA 0/2 : TRANSMIT COMMAND/INDICATE MEMORY ADDRESS
G0
C6/1
D
ANA51 VCI51 V*51 VM51 ANA50 VCI50 V*50 VM50 ANA41 VCI41 V*41 VM41 ANA40 VCI40 V*40 VM40
ANA71 VCI71 V*71 VM71 ANA70 VCI70 V*70 VM70 ANA61 VCI61 V*61 VM61 ANA60 VCI60 V*60 VM60
bit15
bit15
D=0
D=1
bit15
bit15
D
G0
G0
G0
: New Primitive to be transmitted to the selected GCI channel (DOUT4 or DOUT5)
:
: READ C/I MEMORY
: This bit defines one of two GCI multiplexes.
: New Primitive to be transmitted
: Destination; this bit defines the destination of bit 0 to 5.
TDM5
TDM5
READ = 1, READ C/I MEMORY.
READ = 0, WRITE C/I MEMORY.
CA0/2: These bits define one of eight Command/Indicate Channels.
G0 = 0, TDM4 is selected.
G0 = 1, TDM5 is selected.
C6 is transmitted first if ANA = 1.
C4 is transmitted first if ANA = 0.
D=0: the primitive C6 to C1 is transmitted directly into GCI channel defined by G0 and CA 0/2
D=1: the 6 bit word A, E, S1, S2, S3, S4 is put instead of the six bits received latest during the
timeslot 4n+3 (GCI channel defined by G0 and CA 0/2) and transmitted into any selected out-
put timeslot after switching.
New 6 bit word to be transmitted into any output timeslot.
CA2
CA2
CA2
GCI CHANNEL 5
GCI CHANNEL 7
CA1
CA1
CA1
CA0 READ
CA0 READ
CA0 READ
TDM4
TDM4
0
0
0
After reset (00FF)
After reset (0000)
After reset (0000)
bit8
bit8
bit8
bit8
0
0
0
bit7
bit7
bit7
bit7
Nu
Nu
H
H
H
Nu
Nu
TDM5
TDM5
C6/A
C6
A
GCI CHANNEL 6
GCI CHANNEL 8
C5/E C4/S1 C3S2 C2S3 C1S4
C5
E
C4
S1
C3
S2
TDM4
TDM4
GCIR2 (26)
GCIR3 (28)
TCIR (2A)
C2
S3
bit0
bit0
bit0
bit0
C1
S4
H
H
H