STLC5466 STMicroelectronics, STLC5466 Datasheet - Page 56

• Manufacturer Part Number: STLC5466
• Description: RF Wireless Misc Multi-HDLC Sw Matrix
• Manufacturer: STMicroelectronics
• Type: Telecom ICr

Specifications of STLC5466

• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: LQFP-176
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

STLC5466
VI.27 - Initiate Block Address Register 1
A8/23 : Address bits. These 16 bits are the segment address bits of the Initiate Block (A8 to A23 for the
This register concerns the first 32 HDLC Controller 1 named HDLC 1 connected to Din7/Dout7 of the
switching matrix. The Interrupt Queue is common for the first HDLC Controller1 and for the second HDLC
Controller 2. So this register concerns the location of the Interrupt Queue. The location of the Interrupt
Queue is found from the contents of this first IBAR Register 1 (34)
A8/23 : Address bits. These 16 bits are the segment address bits of the Initiate Block (A8 to A23 for the
The Initiate Block Address (IBA1) is:
The 23 more significant bits define one of 8 Megawords. (One word comprises two bytes.)
The least significant bit defines one of two bytes when the microprocessor selects one byte.
Example: MHDLC device address inside
VI.28 - Interrupt Queue Size Register
CS0/1 : Command/Indicate Interrupt Queue Size
MS0/2 : Monitor Channel Interrupt Queue Size
56/130
A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9
TBFS
bit15
bit15
23
A23
A22
0
external memory).The offset is zero (A0 to A7 =”0”).
external memory in the MHDLC address space).The offset is zero (A0 to A7 =”0”).
Initiate Block for HDLC1 address inside
IBAR1 value = (110000 - 100000)/256 = 100H
These two bits define the size of Command/Indicate Interrupt Queue in external memory.
The location is IBA + 256 + HDLC Queue size + Monitor Channel Queue Size (see The Initiate
Block Address (IBA)).
These three bits define the size of Monitor Channel Interrupt Queue in external memory.
The location is IBA + 256 + HDLC Queue size.
A21
0
A20
0
A19
0
A18
0
A17
0
P mapping = 100000H
After reset (0000)
After reset (0000)
A16
bit8
bit8
0
P mapping = 110000H
HS2
A15
bit7
bit7
H
H
HS1
A14
H
HS0
A13
.
A8
MS2
A12
8
7
0
MS1
A11
0
0
MS0
A10
0
0
IBAR1 (34)
CS1
IQSR (36)
A9
0
0
CS0
bit0
bit0
A8
0
0
H
H