M29W256GH7AN6E NUMONYX, M29W256GH7AN6E Datasheet - Page 68

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M29W256GH7AN6E

Manufacturer Part Number
M29W256GH7AN6E
Description
Flash Mem Parallel 3V/3.3V 256M-Bit 32M x 8/16M x 16 70ns 56-Pin TSOP Tray
Manufacturer
NUMONYX
Datasheet

Specifications of M29W256GH7AN6E

Package
56TSOP
Cell Type
NOR
Density
256 Mb
Architecture
Sectored
Block Organization
Symmetrical
Location Of Boot Block
Bottom|Top
Typical Operating Supply Voltage
3|3.3 V
Sector Size
128KByte x 256
Timing Type
Asynchronous
Operating Temperature
-40 to 85 °C
Interface Type
Parallel

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Figure 18. Chip enable controlled program waveforms (8-bit mode)
1. Only the third and fourth cycles of the Program command are represented. The Program command is followed by the check
2. PA is the address of the memory location to be programmed. PD is the data to be programmed.
3. DQ7 is the complement of the data bit being programmed to DQ7 (see
4. See
68/97
of status register data polling bit.
and
Table 28: Read AC characteristics
Table 29: Write AC characteristics, write enable
DQ0-DQ7
A0-A23/
A–1
W
G
E
for details on the timings.
tAVAV
tWLEL
tGHEL
tDVEH
tELEH
3rd cycle
tAVEL
555h
controlled,
AOh
4th cycle
tEHWH
tEHDX
PA
Table 30: Write AC characteristics, chip enable controlled
tEHEL1
PD
Section 7.1: Data polling bit
tELAX
tWHWH1
Data Polling
PA
DQ7
D OUT
AI13334
(DQ7)).

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