M29W256GH7AN6E NUMONYX, M29W256GH7AN6E Datasheet
M29W256GH7AN6E
Specifications of M29W256GH7AN6E
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M29W256GH7AN6E Summary of contents
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... Low power consumption – Standby and automatic standby Minimum 100,000 program/erase cycles per block RoHS compliant packages Automotive device grade: Temperature -40 ° °C (Automotive grade certified) 208012-05 M29W256GH M29W256GL BGA FBGA (ZS BGA TBGA64 (ZA Device code 227Eh + 2222h + 2201 www.numonyx.com 1/97 1 ...
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Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Software protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Volatile protection mode command set . . . . . . . . . . . . . . . . . . . . . . . . . 45 6.4.4 Non-volatile protection mode command set . . ...
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List of tables Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of figures Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Description The M29W256GH and M29W256GL are 256-Mbit (16 Mbit x16 or 32 Mbit x8) non-volatile flash memories that can be read, erased and reprogrammed. These operations can be performed using a single low voltage (2.7 to 3.6 V) supply. ...
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Table 2. Signal names Name A0-A23 DQ0-DQ7 DQ8-DQ14 DQ15A− BYTE V CCQ V CC ( /WP may be left floating internally connected to a ...
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Figure 2. TSOP connections V PP /WP A23 1 56 A22 A15 A14 A13 A12 A11 A10 A9 A8 A19 A20 M29W256GH 15 42 A21 M29W256GL RB A18 A17 ...
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Figure 3. TBGA and FBGA connections (top view through package CCQ 10/ ...
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Figure 4. Block addresses (x8) Address lines A23-A0, DQ15A-1 FF0000h 128 Kbytes 03FFFFh 128 Kbytes 020000h 01FFFFh 128 Kbytes 000000h (x16) Address lines A23-A0 FFFFFFh 64 Kwords 64 Kwords 00FFFFh 64 Kwords 000000h Total of 256 uniform blocks AI13332 11/97 ...
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Signal descriptions See Figure 1: Logic connected to this device. 2.1 Address inputs (A0-A23) The address inputs select the cells in the memory array to access during bus read operations. During bus write operations they control the commands sent ...
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Write enable (W) The write enable pin, W, controls the bus write operation of the memory’s command interface. 2.8 V /write protect (V PP The V /write protect pin provides two functions. The V PP use an external high ...
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Reset (RP) The reset pin can be used to apply a hardware reset to the memory. A hardware reset is achieved by holding reset Low, V High the memory will be ready for bus read and bus ...
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V ground the reference for all voltage measurements. The device features two V SS which must be connected to the system ground. pins both of SS 15/97 ...
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Bus operations There are five standard bus operations that control the device. These are bus read (random and page modes), bus write, output disable, standby and automatic standby. See Table 4: Bus operations, 8-bit mode summary. Typical glitches of ...
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Reset During reset mode the memory is deselected and the outputs are high impedance. The memory is in reset mode when standby level, independently from the chip enable, output enable or write enable inputs. 3.6 ...
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Read electronic signature The memory has two codes, the manufacturer code and the device code used to identify the memory. These codes can be accessed by performing read operations with control signals and addresses set as shown in programmer ...
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M Table 4. Bus operations, 8-bit mode (1) Operation E G Bus read Bus write Standby Output disable Reset ...
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Table 6. Read electronic signature - auto select mode - programmer method (8-bit mode) Read (1) cycle A23-A10 A9 A8-A7 A6 A5- DQ15A-1 DQ14-DQ8 Manufacturer code Device code (cycle ...
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Table 8. Block protection - auto select mode - programmer method (8-bit mode) (1) Operation E G Verify M29W256GL extended memory block protection M29W256GH indicator (bit DQ7) Verify block protection status ...
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Hardware protection The M29W256GH and M29W256GL feature a V lowest block. Refer to 5 Software protection The M29W256GH and M29W256GL have three different software protection modes: Volatile protection Non-volatile protection Password protection On first use all parts default to ...
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Volatile protection mode The volatile protection allows the software application to easily protect blocks against inadvertent change. However, the protection can be easily disabled when changes are needed. Volatile protection bits, VPBs, are volatile and unique for each block ...
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Refer to Table 11: Block protection status details on the block protection mechanism, and to volatile protection mode command set. 5.2.2 Non-volatile protection bit lock bit The non-volatile protection bit lock bit (NVPB lock bit global volatile bit ...
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Figure 5. Software protection scheme Parameter block or main block Volatile protection Non-volatile protection 1. NVPBs default to ‘1’ (block unprotected) after power-up and hardware reset. A block is protected or unprotected when its NVPB is set to ‘0’ and ...
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Non-volatile protection mode lock bit (DQ1) The non-volatile protection mode lock bit, DQ1, is one-time programmable. Programming (change the first apex to ‘0’) this bit permanently places the device in non-volatile protection mode. By default the memory operates in ...
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If the block NVPB is set to ‘0’, the block is protected, if set to ‘1’ unprotected the block VPB is set to ‘0’, the block is protected, if set to ‘1’ unprotected. ...
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Command interface All bus write operations to the memory are interpreted by the command interface. Commands consist of one or more sequential bus write operations. Failure to observe a valid sequence of bus write operations will result in the ...
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Read CFI Query command The memory contains an information area, named CFI data structure, which contains a description of various electrical and timing parameters, density information and functions supported by the memory. See Table 43 and Table 44 (CFI) ...
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Six bus write operations are required to select the first block in the list. Each additional block in the list can be selected by repeating the sixth bus write operation using the address of the additional block. After the command ...
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During erase suspend a bus read operation to the extended memory block will output the extended memory block data. Once in the extended block mode, the Exit Extended Block command must be issued before the erase operation can be resumed. ...
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Program Suspend command The Program Suspend command allows the system to interrupt a program operation so that data can be read from any block. When the Program Suspend command is issued during a program operation, the device suspends the ...
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Table 12. Standard commands, 8-bit mode Command 1 Read/Reset 3 Manufacturer code Device code Extended memory Auto 3 block protection Select indicator Block protection status (4) Program 4 Chip Erase 6 Block Erase 6+ Erase/Program Suspend 1 Erase/Program Resume 1 ...
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Table 13. Standard commands, 16-bit mode Command 1 Read/Reset 3 Manufacturer code Device code Extended memory Auto 3 block protection Select indicator Block protection status (4) Program 4 Chip Erase 6 Block Erase 6+ Erase/Program Suspend 1 Erase/Program Resume 1 ...
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Unlock Bypass command The Unlock Bypass command is used to place the device in unlock bypass mode. When the device enters the unlock bypass mode, the two initial unlock cycles required in the standard program command sequence are no ...
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Unlock Bypass Chip Erase command The Unlock Bypass Chip Erase command can be used to erase all memory blocks at a time. The command requires two bus write operations only instead of six using the standard Chip Erase command. ...
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Table 15. Unlock Bypass commands, 16-bit mode Command Unlock Bypass Unlock Bypass Program Unlock Bypass Block Erase Unlock Bypass Chip Erase Unlock Bypass Reset 1. X don't care, PA program address, PD program data, BAd any address in the block, ...
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Write to Buffer Program command Five successive steps are required to issue the Write to Buffer Program command: 1. The Write to Buffer Program command starts with two unlock cycles 2. The third bus write cycle sets up the Write ...
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Table 16. Write to buffer commands, 8-bit mode Command Write to Buffer Program N+5 AAA Unlock Bypass Write to N+3 BAd Buffer Program Write to Buffer Program 1 Confirm Buffered Program Abort 3 Reset 1. X don’t care, PA program ...
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Buffered Program Abort Reset command A Buffered Program Abort Reset command must be issued to reset the error condition and return to read mode. One of the erase commands must be used to set all the bits in a block ...
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Enhanced Buffered Exit command The Enhanced Buffered Exit command is used to return the device to read mode; before this command any other command, except the Enhanced Buffered Program command set, is ignored. Two bus write operations are required to ...
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The enhanced buffered programming sequence can be aborted in the following ways: Write to an address in a block different than the one specified during the buffer load. Write an address/data pair to a different buffer-page than the one selected ...
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Protection commands Blocks can be protected individually against accidental program, erase or read operations. The device block protection scheme is shown in either Table 19, or summary of the block protection commands. Block protection commands are available both in ...
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The device remains in extended memory block mode until the Exit Extended Memory Block command is issued or power is removed from the device. After power- hardware reset, the device reverts to read mode, and the commands issued ...
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Volatile protection mode command set Enter Volatile Protection Command Set command Three bus write cycles are required to issue the Enter Volatile Protection Command Set command. Once the command has been issued, only the commands related to the volatile ...
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Figure 7. NVPB program/erase algorithm 46/97 Enter NVPB command set. Program NVPB Addr = BAd Read Byte twice Addr = BAd NO DQ6= Toggle YES NO DQ5=1 Wait 500 μs YES Read Byte twice Addr = BAd NO DQ6= Read ...
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NVPB lock bit command set Enter NVPB Lock Bit Command Set command Three bus write cycles are required to issue the Enter NVPB Lock Bit Command Set command. Once the command has been issued, the only commands allowing to ...
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To verify the 64-bit password, the complete command sequence must be entered eight times at eight consecutive addresses selected by A1-A0 plus DQ15A-1 in 8-bit mode, or four times at four consecutive addresses selected by A1-A0 in 16-bit mode. If ...
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Table 19. Block protection commands, 8-bit mode Command 1st 2nd Ad Data Ad Data Enter Lock Register 3 AAA AA 555 55 Command (4) Set Lock Register DATA (5) Program Lock Register DATA 1 X (5) ...
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Ad address, Dat data, BAd any address in the block, RD read data, PWDn password byte PWAn password address ( 7), X don’t care. All values in the table are in hexadecimal. 2. ...
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Table 20. Block protection commands, 16-bit mode Command 1st Ad Enter Lock Register 3 555 (4) Command Set Lock Register Program 2 X Lock Register Read 1 X Enter Volatile Protection 3 555 Command Set VPB Program 2 X Read ...
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Table 21. Program/erase times and program/erase endurance cycles Parameter Chip Erase Chip Erase (4) (5) Block Erase (128 kbytes) Erase Suspend latency time Block Erase timeout Single Byte Program Byte Program Write to Buffer Program (64 bytes at-a-time) Single Word ...
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Status register The M29W256GH/L has one status register. The various bits convey information and errors on the current and previous program/erase operation. Bus read operations from any address within the memory, always read the status register during program and ...
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Error bit (DQ5) The error bit can be used to identify errors detected by the program/erase controller. The error bit is set to ’1’ when a program, block erase or chip erase operation fails to write the correct data ...
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Table 22. Status register bits Operation Program Program during erase suspend Enhanced Buffered Program Entry Buffered program abort Program error Chip erase Block erase before timeout Block erase Erase suspend Erase error 1. Unspecified data bits should be ignored. (1) ...
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Figure 8. Data polling flowchart 56/97 START READ DQ5 & DQ7 at VALID ADDRESS DQ7 YES = DATA NO NO DQ5 = 1 YES READ DQ7 at VALID ADDRESS DQ7 YES = DATA NO FAIL PASS AI07760 ...
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Figure 9. Data toggle flowchart START READ DQ6 at Valid Address READ DQ5 & DQ6 at Valid Address DQ6 NO = TOGGLE YES NO DQ5 = 1 YES READ DQ6 TWICE at Valid Address DQ6 NO = TOGGLE YES FAIL ...
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Maximum ratings Stressing the device above the rating listed in cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. These are stress ratings only and operation of the device ...
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DC and AC parameters This section summarizes the operating measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristics tables that follow, are derived from tests performed under the measurement ...
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Figure 11. AC measurement I/O waveform V CCQ 0 V Table 25. Power-up waiting timings Symbol ( High to Chip Enable Low VCHEL CC ( High to Chip Enable Low VCQHEL CCQ t V High to ...
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Table 26. Device capacitance Symbol Parameter C Input capacitance IN C Output capacitance OUT 1. Sampled only, not 100% tested. Table 27. DC characteristics Symbol Parameter (1) I Input leakage current LI I Output leakage current LO Random read I ...
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Figure 13. Random read AC waveforms (8-bit mode) A0-A23/ A– DQ0-DQ7 BYTE tELBL/tELBH Note: BYTE = V IL Figure 14. Random read AC waveforms (16-bit mode) A0-A23 E G DQ0-DQ14, DQ15A–1 BYTE tELBL/tELBH Note: BYTE = V IH ...
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Figure 15. Page read AC waveforms (16-bit mode) 63/97 ...
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Table 28. Read AC characteristics Symbol Alt. Parameter Address Valid to Next t t AVAV RC Address Valid Address Valid to Output t t AVQV ACC Valid Address Valid to Output t t AVQV1 PAGE Valid (page) Chip Enable Low ...
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Figure 16. Write enable controlled program waveforms (8-bit mode) tAVAV A0-A23 A-1 tELWL E tGHWL G tWLWH W tDVWH DQ0-DQ7 1. Only the third and fourth cycles of the Program command are represented. The Program command is followed by the ...
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Figure 17. Write enable controlled program waveforms (16-bit mode) tAVAV A0-A23 tELWL E tGHWL G tWLWH W tDVWH DQ0-DQ1', DQ15A–1 1. Only the third and fourth cycles of the Program command are represented. The Program command is followed by the ...
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M Table 29. Write AC characteristics, write enable controlled Symbol Alt t t Address Valid to Next Address Valid AVAV Chip Enable Low to Write Enable Low ELWL Write Enable Low to Write Enable ...
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Figure 18. Chip enable controlled program waveforms (8-bit mode) A0-A23/ A– DQ0-DQ7 1. Only the third and fourth cycles of the Program command are represented. The Program command is followed by the check of status register data ...
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Figure 19. Chip enable controlled program waveforms (16-bit mode) A0-A23 DQ0-DQ14 A–1 1. Only the third and fourth cycles of the Program command are represented. The Program command is followed by the check of status register data ...
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Figure 20. Chip/block erase waveforms (8-bit mode) tAVAV A0-A23/ A–1 tELWL E tGHWL G tWLWH W tDVWH DQ0-DQ7 1. For a Chip Erase command, addresses and data are 555h and 10h, respectively, while they are BAd and 30h for a ...
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Figure 21. Reset AC waveforms (no program/erase ongoing tPLPX Figure 22. Reset during program/erase operation AC waveforms tPLPX Table 31. Reset AC characteristics Symbol Alt. t (2) READ t RP ...
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Figure 23. Accelerated program timing waveforms V PPH tVHVPP Figure 24. Data polling AC waveforms tWHEH DQ7 DATA DQ6-DQ0 DATA R/B 1. DQ7 returns valid data bit when the ...
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Figure 25. Toggle/alternative toggle bit polling AC waveforms (8-bit mode) A0-A23/ A–1 E tWHGL2 W G tWHDX DQ6/DQ2 Data tWHRL R/B 1. DQ6 stops toggling when the ongoing Program or Erase command is completed. DQ2 stops toggling when the ongoing ...
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... Package mechanical In order to meet environmental requirements, Numonyx offers these devices in RoHS compliant packages. RoHS compliant packages are lead-free. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. Figure 26. TSOP56 – ...
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Figure 27. TBGA64 active ball array pitch, package outline BALL "A1" Drawing is not to scale. Table 34. TBGA64 ...
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Figure 28. FBGA64 mm— active ball array pitch, package outline E BALL "A1" 1. Drawing is not to scale. Table 35. FBGA64 mm— active ball array ...
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... Note: This product is also available with the extended memory block factory locked. For further details and ordering information contact your nearest Numonyx sales office. Devices are shipped from the factory with the memory content bits erased to ’1’. For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest Numonyx sales office ...
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Appendix A Block addresses and read/modify protection groups Table 37 shows block addresses 0-127. Table 37. Block addresses 0 - 127 (page Block Protection group 0 Protection group 1 Protection group 2 Protection group 3 Protection group ...
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Table 37. Block addresses 0 - 127 (page Block Protection group 29 Protection group 30 Protection group 31 Protection group 32 Protection group 33 Protection group 34 Protection group 35 Protection group 36 Protection group 37 Protection ...
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Table 37. Block addresses 0 - 127 (page Block Protection group 62 Protection group 63 Protection group 64 Protection group 65 Protection group 66 Protection group 67 Protection group 68 Protection group 69 Protection group 70 Protection ...
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Table 37. Block addresses 0 - 127 (page Block Protection group 95 Protection group 96 Protection group 97 Protection group 98 Protection group 99 Protection group 100 Protection group 101 Protection group 102 Protection group 103 Protection ...
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Table 38. Block addresses 128 - 255 (page Block Block size, x8 128 128 129 128 130 128 131 128 132 128 133 128 134 128 135 128 136 128 137 128 138 128 139 128 140 ...
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Table 38. Block addresses 128 - 255 (page Block Block size, x8 Block size, x16 162 128 163 128 164 128 165 128 166 128 167 128 168 128 169 128 170 128 171 128 172 128 ...
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Table 38. Block addresses 128 - 255 (page Block Block size, x8 196 128 197 128 198 128 199 128 200 128 201 128 202 128 203 128 204 128 205 128 206 128 207 128 208 ...
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Table 38. Block addresses 128 - 255 (page Block Block size, x8 Block size, x16 230 128 231 128 232 128 233 128 234 128 235 128 236 128 237 128 238 128 239 128 240 128 ...
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... A0-A7) used to retrieve the data. The CFI data structure also contains a security area where a 64-bit unique security number is written (see accessed only in read mode by the final user impossible to change the security number after it has been written by Numonyx. Table 39. Query structure overview ...
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Table 41. CFI query system interface information Address Data x16 x8 1Bh 36h 0027h 1Ch 38h 0036h 1Dh 3Ah 00B5h 1Eh 3Ch 00C5h 1Fh 3Eh 0004h 20h 40h 0004h 21h 42h 0009h 22h 44h 0011h 23h 46h 0004h 24h 48h ...
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Table 42. Device geometry definition Address Data x16 x8 27h 4Eh 0019h Device size = 2 28h 50h 0002h Flash device interface code description 29h 52h 0000h 2Ah 54h 0006h Maximum number of bytes in multiple-byte program or page= 2 ...
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Table 43. Primary algorithm-specific extended query table Address Data x16 x8 40h 80h 0050h 41h 82h 0052h 42h 84h 0049h 43h 86h 0031h 44h 88h 0033h 45h 8Ah 0010h 46h 8Ch 0002h 47h 8Eh 0001h 48h 90h 0000h 49h 92h ...
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Table 44. Security code area Address Data x16 x8 61h C3h, C2h XXXX 62h C5h, C4h XXXX 63h C7h, C6h XXXX 64h C9h, C8h XXXX 90/97 Description 64-bit: unique device number ...
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Appendix C Extended memory block The M29W256GH/L has an extra block, the extended memory block, that can be accessed using a dedicated command. This extended memory block is 128 words mode and 256 bytes ...
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C.2 Customer lockable extended memory block A device where the extended memory block is customer lockable is delivered with the DQ7 bit set to ‘0’ and the extended memory block unprotected the customer to program and ...
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Appendix D Flowcharts Figure 29. Write to buffer program flowchart and pseudocode 1. n+1 is the number of addresses to be programmed write to buffer program abort and reset must be issued to return the device in read ...
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Figure 30. Enhanced buffered program flowchart and pseudocode Start Enhanced Buffered Program command set Read DQ6 at valid address Read DQ5 & DQ6 at valid address DQ6 = No toggle Yes No DQ5=1 Yes Read DQ6 twice at valid address ...
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When the block address is specified, all the addresses in the selected block address space must be issued starting from (00). Furthermore, when loading write buffer address with data, data program addresses must be consecutive. 3. DQ7 must be ...
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Revision history Table 46. Document revision history Date 24-Nov-2008 25-March-2009 20-May-2009 19-June-2009 19-January-2010 96/97 Version 01 Initial release. Revised data in the following tables: – Table 21: Program/erase times and program/erase endurance cycles; – Table 27: DC characteristics; – ...
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... NUMONYX PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Numonyx products are not intended for use in medical, life saving, life sustaining, critical control or safety systems nuclear facility Numonyx may make changes to specifications and product descriptions at any time, without notice. ...