M29W256GH7AN6E NUMONYX, M29W256GH7AN6E Datasheet - Page 65

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M29W256GH7AN6E

Manufacturer Part Number
M29W256GH7AN6E
Description
Flash Mem Parallel 3V/3.3V 256M-Bit 32M x 8/16M x 16 70ns 56-Pin TSOP Tray
Manufacturer
NUMONYX
Datasheet

Specifications of M29W256GH7AN6E

Package
56TSOP
Cell Type
NOR
Density
256 Mb
Architecture
Sectored
Block Organization
Symmetrical
Location Of Boot Block
Bottom|Top
Typical Operating Supply Voltage
3|3.3 V
Sector Size
128KByte x 256
Timing Type
Asynchronous
Operating Temperature
-40 to 85 °C
Interface Type
Parallel

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Figure 16. Write enable controlled program waveforms (8-bit mode)
1. Only the third and fourth cycles of the Program command are represented. The Program command is followed by the check
2. PA is the address of the memory location to be programmed. PD is the data to be programmed.
3. DQ7 is the complement of the data bit being programmed to DQ7 (see
4.
of status register data polling bit and by a read operation that outputs the data, DOUT, programmed by the previous
Program command.
SeeTable 29: Write AC characteristics, write enable
and
Table 28: Read AC characteristics
DQ0-DQ7
A-1
A0-A23
E
G
W
tAVAV
tGHWL
tELWL
tWLWH
tDVWH
3rd cycle
for details on the timings.
tAVWL
555h
AOh
4th cycle
tWHDX
tWHEH
PA
controlled,
tWHWL
PD
tWLAX
Table 30: Write AC characteristics, chip enable controlled
tWHWH1
Data Polling
Section 7.1: Data polling bit
PA
DQ7
D OUT
tAVAV
tGHQZ
Read cycle
D OUT
tELQV
(DQ7)).
tGLQV
tAXQX
AI13333
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