DS33R41 Maxim Integrated Products, DS33R41 Datasheet - Page 71

• Manufacturer Part Number: DS33R41
• Description: Network Controller & Processor ICs Inverse-Multiplexing Ethernet Mapper wit
• Manufacturer: Maxim Integrated Products

10.4.3 T1 Receive-Side Digital-Milliwatt Code Generation
Receive-side
(TR.T1RDMR1/2/3) to determine which of the 24 T1 channels of the T1 line going to the backplane should be
overwritten with a digital-milliwatt pattern. The digital-milliwatt code is an 8-byte repeating pattern that represents a
1kHz sine wave (1E/0B/0B/1E/9E/8B/8B/9E). Each bit in the TR.T1RDMRx registers represents a particular
channel. If a bit is set to a 1, then the receive data in that channel is replaced with the digital-milliwatt code. If a bit
is set to 0, no replacement occurs.
Table 10-2. T1 Alarm Criteria
Blue Alarm (AIS)
(Note 1)
Yellow
Alarm
(RAI)
Red Alarm (LRCL)
(Also referred to as loss of signal)
Note 1: The definition of Blue Alarm (or AIS) is an unframed all-ones signal. Blue Alarm detectors should be able to operate properly in the
Note 2: ANSI specifications use a different nomenclature than this document. The following terms are equivalent:
presence of a 10E-3 error rate and they should not falsely trigger on a framed all-1s signal. Blue Alarm criteria in the device has been
set to achieve this performance. It is recommended that the RBL bit be qualified with the RLOS bit.
RBL = AIS
RCL = LOS
RLOS = LOF
RYEL = RAI
D4 Bit 2 Mode
(TR.T1RCR2.0 = 0)
D4 12th F-Bit Mode
(TR.T1RCR2.0 = 1;
this mode is also
referred to as the
“Japanese Yellow
Alarm”)
ESF Mode
ALARM
digital-milliwatt
DS33R41 Inverse-Multiplexing Ethernet Mapper with Quad Integrated T1/E1/J1 Transceivers
code
When bit 2 of 256 consecutive
channels is set to 0 for at least 254
occurrences
When the 12th framing bit is set to 1
for two consecutive occurrences
00FF appear in the FDL
When over a 3ms window, five or
fewer 0s are received
When 16 consecutive patterns of
When 192 consecutive 0s are
received
generation
SET CRITERIA
71 of 335
involves
using
the
When over a 3ms window, six or
more 0s are received
When bit 2 of 256 consecutive
channels is set to 0 for fewer than
254 occurrences
When the 12th framing bit is set to 0
for two consecutive occurrences
When 14 or fewer patterns of 00FF
hex out of 16 possible appear in the
FDL
When 14 or more 1s out of 112
possible bit positions are received
receive
CLEAR CRITERIA
digital-milliwatt
registers