DS33R41 Maxim Integrated Products, DS33R41 Datasheet - Page 257
DS33R41
Manufacturer Part Number
DS33R41
Description
Network Controller & Processor ICs Inverse-Multiplexing Ethernet Mapper wit
Manufacturer
Maxim Integrated Products
Datasheet
1.DS33R41.pdf
(335 pages)
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Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 7 to 0: Receive Channels 16 to 9 Channel Blocking Control Bits (CH16 to CH9)
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 7 to 0: Receive Channels 24 to 17 Channel Blocking Control Bits (CH24 to CH17)
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 7 to 0: Receive Channels 32 to 25 Channel Blocking Control Bits (CH32 to CH25)
0 = force the RCHBLK pin to remain low during this channel time
1 = force the RCHBLK pin high during this channel time
0 = force the RCHBLK pin to remain low during this channel time
1 = force the RCHBLK pin high during this channel time
0 = force the RCHBLK pin to remain low during this channel time
1 = force the RCHBLK pin high during this channel time
CH16
CH24
CH32
7
0
7
0
7
0
TR.RCBR2
Receive Channel Blocking Register 2
89h
TR.RCBR3
Receive Channel Blocking Register 3
8Ah
TR.RCBR4
Receive Channel Blocking Register 4
8Bh
CH15
CH23
CH31
6
0
6
0
6
0
CH14
CH22
CH30
5
0
5
0
5
0
257 of 335
CH13
CH21
CH29
4
0
4
0
4
0
CH12
CH20
CH28
3
0
3
0
3
0
CH11
CH19
CH27
2
0
2
0
2
0
CH10
CH18
CH26
1
0
1
0
1
0
CH17
CH25
CH9
0
0
0
0
0
0
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