DS33R41 Maxim Integrated Products, DS33R41 Datasheet - Page 320
DS33R41
Manufacturer Part Number
DS33R41
Description
Network Controller & Processor ICs Inverse-Multiplexing Ethernet Mapper wit
Manufacturer
Maxim Integrated Products
Datasheet
1.DS33R41.pdf
(335 pages)
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14.10 AC Characteristics—Receive Side
Table 14-15. AC Characteristics—Receive Side
(V
RCLKn Period
RCLKn Pulse Width
RCLKn Pulse Width
RCLKI Period
RCLKI Pulse Width
RSYSCLK Period
RSYSCLK Pulse Width
RSYNC Setup to RSYSCLK Falling
RSYNC Pulse Width
RPOSI/RNEGI Setup to RCLKI Falling
RPOSI/RNEGI Hold from RCLKI
Falling
RSYSCLK, RCLKI Rise and Fall Times
Delay RCLKn to RPOSO, RNEGO
Valid
Delay RCLKn to RSERO, RDATA,
RSIG Valid
Delay RCLKn to RCHCLK, RSYNC,
RCHBLK, RFSYNC
Delay RSYSCLK to RSERO, RSIG
Valid
Delay RSYSCLK to RCHCLK, CHBLK,
RMSYNC, RSYNC
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
DD
= 3.3V ±5%, T
Timing parameters in this table are guaranteed by design (GBD).
Jitter attenuator enabled in the receive path.
Jitter attenuator disabled or enabled in the transmit path.
RSYSCLK = 1.544MHz.
RSYSCLK = 2.048MHz.
RSYSCLK = 4.096MHz.
RSYSCLK = 8.192MHz.
RSYSCLK = 16.384MHz.
PARAMETER
A
= -40°C to +85°C.) (Note 1)
SYMBOL
t
R
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
PW
CP
CH
SP
SH
SU
SU
HD
DD
LP
LH
LH
CL
SL
, t
D1
D2
D3
D4
LL
LL
F
320 of 335
(Figure 14-14
(Note 2)
(Note 2)
(Note 3)
(Note 3)
(Note 4)
(Note 5)
(Note 6)
(Note 7)
(Note 8)
CONDITIONS
to
Figure
MIN
200
200
150
150
20
20
20
20
20
50
20
20
14-18)
488 (E1)
648 (T1)
488 (E1)
648 (T1)
0.5 t
0.5 t
0.5 t
0.5 t
0.5 t
0.5 t
0.5 t
0.5 t
TYP
648
488
244
122
61
CP
CP
SP
SP
LP
LP
LP
LP
MAX
22
50
50
50
22
22
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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