DS33R41 Maxim Integrated Products, DS33R41 Datasheet - Page 60

• Manufacturer Part Number: DS33R41
• Description: Network Controller & Processor ICs Inverse-Multiplexing Ethernet Mapper wit
• Manufacturer: Maxim Integrated Products

9.13.3 PHY MII Management Block and MDIO Interface
The MII Management Block allows for the host to control up to 32 PHYs, each with 32 registers. The MII block
communicates with the external PHY using 2-wire serial interface composed of MDC (serial clock) and MDIO for
data. The MDIO data is valid on the rising edge of the MDC clock. The Frame format for the MII Management
Interface is shown
SU.MACMIIA MII Management Address Register and data is passed through the indirect SU.MACMIID Data
Register. These indirect registers are accessed through the MAC Control Registers defined in
clock is internally generated and runs at 1.67MHz. Note that the device provides a single MII Management port,
and all control registers for this function are located in MAC 1.
Figure 9-11. MII Management Frame
READ
WRITE
Preamble
111...111
111...111
Figure
32 bits
9-11. The read/write control of the MII Management is accomplished through the indirect
2 bits
Start
01
01
Opco
2 bits
de
10
01
Phy Adrs
PHYA[4:0]
PHYA[4:0]
5 bits
60 of 335
PHYR[4:0]
PHYR[4:0]
Phy Reg
5 bits
Aroun
2 bits
Turn
ZZ
10
d
ZZZZZZZZZ
PHYD[15:0]
bits
Data
16
Idle
Bit
Z
Z
1
Table
9-8. The MDC