DS33R41 Maxim Integrated Products, DS33R41 Datasheet - Page 148

• Manufacturer Part Number: DS33R41
• Description: Network Controller & Processor ICs Inverse-Multiplexing Ethernet Mapper wit
• Manufacturer: Maxim Integrated Products

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 0: Transmit Errored Packet Insertion Finished (TEPF). This bit is set when the number of errored packets
indicated by the TPEN[7:0] bits in the TEPC register have been transmitted. This bit is cleared when errored
packet insertion is disabled, or a new errored packet insertion process is initiated.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 0: Transmit Errored Packet Insertion Finished Latched (TEPFL). This bit is set when the TEPF bit in the
TPPSR register transitions from 0 to 1.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 0: Transmit Errored Packet Insertion Finished Interrupt Enable (TEPFIE). This bit enables an interrupt if
the TEPFL bit in the LI.TPPSRL register is set.
0 = interrupt disabled
1 = interrupt enabled
—
—
—
7
0
7
7
0
—
—
—
6
0
6
6
0
LI.TPPSR
Transmit Packet Processor Status Register
0C8h
LI.TPPSRL
Transmit Packet Processor Status Register Latched
0C9h
LI.TPPSRIE
Transmit Packet Processor Status Register Interrupt Enable
0CAh
—
—
—
5
0
5
5
0
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—
—
—
0
0
4
4
4
—
—
—
3
0
3
3
0
—
—
—
2
0
2
2
0
—
—
—
1
0
1
1
0
TEPFIE
TEPFL
TEPF
0
0
0
0
0