DS33R41 Maxim Integrated Products, DS33R41 Datasheet - Page 66
DS33R41
Manufacturer Part Number
DS33R41
Description
Network Controller & Processor ICs Inverse-Multiplexing Ethernet Mapper wit
Manufacturer
Maxim Integrated Products
Datasheet
1.DS33R41.pdf
(335 pages)
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For the transmitter if X.86 is enabled the sequence of processing is as follows:
Note that the Serial transmit and receive registers apply to the X.86 implementations with specific exceptions. The
exceptions are outlined in the Serial Interface transmit and receive register sections.
The X86 received frame is aborted if:
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Construct frame including start flag SAPI, Control and MAC frame
Calculate FCS
Perform transparency processing - 7E is translated to 7D5E, 7D is translated to 7D5D
Append the end flag(7E)
Scramble the sequence X
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If 7d,7E is detected. This is an abort packet sequence in X.86
Invalid FCS is detected
The received frame has less than 6 octets
Control, SAPI and address field are mismatched to the programmed value
Octet 7d and octet other than 5d, 5e, 7e, or dd is detected
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