DS33R41 Maxim Integrated Products, DS33R41 Datasheet - Page 256
DS33R41
Manufacturer Part Number
DS33R41
Description
Network Controller & Processor ICs Inverse-Multiplexing Ethernet Mapper wit
Manufacturer
Maxim Integrated Products
Datasheet
1.DS33R41.pdf
(335 pages)
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Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 7 to 0: Receive Channels 16 to 9 Code Insertion Control Bits (CH16 to CH9)
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 7 to 0: Receive Channels 24 to 17 Code Insertion Control Bits (CH24 to CH17)
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 7 to 0: Receive Channels 32 to 25 Code Insertion Control Bits (CH32 to CH25)
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 7 to 0: Receive Channels 8 to 1 Channel Blocking Control Bits (CH8 to CH1)
0 = do not insert data from the idle-code array into the receive data stream
1 = insert data from the idle-code array into the receive data stream
0 = do not insert data from the idle-code array into the receive data stream
1 = insert data from the idle-code array into the receive data stream
0 = do not insert data from the idle-code array into the receive data stream
1 = insert data from the idle-code array into the receive data stream
0 = force the RCHBLK pin to remain low during this channel time
1 = force the RCHBLK pin high during this channel time
CH16
CH24
CH32
CH8
7
0
7
0
7
0
7
0
TR.RCICE2
Receive-Channel Idle-Code Enable Register 2
85h
TR.RCICE3
Receive-Channel Idle-Code Enable Register 3
86h
TR.RCICE4
Receive-Channel Idle-Code Enable Register 4
87h
TR.RCBR1
Receive Channel Blocking Register 1
88h
CH15
CH23
CH31
CH7
6
0
6
0
6
0
6
0
CH14
CH22
CH30
CH6
5
0
5
0
5
0
5
0
256 of 335
CH13
CH21
CH29
CH5
4
0
4
0
4
0
4
0
CH12
CH20
CH28
CH4
3
0
3
0
3
0
3
0
CH11
CH19
CH27
CH3
2
0
2
0
2
0
2
0
CH10
CH18
CH26
CH2
1
0
1
0
1
0
1
0
CH17
CH25
CH9
CH1
0
0
0
0
0
0
0
0
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