DS33R41 Maxim Integrated Products, DS33R41 Datasheet - Page 133
DS33R41
Manufacturer Part Number
DS33R41
Description
Network Controller & Processor ICs Inverse-Multiplexing Ethernet Mapper wit
Manufacturer
Maxim Integrated Products
Datasheet
1.DS33R41.pdf
(335 pages)
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Bit 4: Serial Interface 1 TX Interrupt Enable (LINE1TIE). Setting this bit to 1 enables an interrupt on LIN1TIS.
Bit 0: Serial Interface 1 RX Interrupt Enable (LINE1RIE). Setting this bit to 1 enables an interrupt on LIN1RIS.
Bit 4: Serial Interface 1 TX Interrupt Status (LIN1TIS). This bit is set if Serial Interface 1 Transmit has an
enabled interrupt generating event. Serial Interface interrupts consist of HDLC interrupts and X.86 interrupts.
Bit 0: Serial Interface 1 RX Interrupt Status (LIN1RIS). This bit is set if Serial Interface 1 Receive has an
enabled interrupt generating event. Serial Interface interrupts consist of HDLC interrupts and X.86 interrupts.
Bit 0: Ethernet Interface 1 Interrupt Enable (SUB1IE). Setting this bit to 1 enables an interrupt on SUB1S.
Bit 0: Ethernet Interface 1 Interrupt Status (SUB1IS). This bit is set to 1 if Ethernet Interface 1 has an enabled
interrupt generating event. The Ethernet Interface consists of the MAC and The RMII/MII port.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Bit #
Name
Default
Register Name:
Register Description:
Register Address:
Register Name:
Register Description:
Register Address:
—
—
—
—
7
0
7
0
7
0
7
0
—
—
—
—
6
0
6
0
6
0
6
0
GL.LIS
Global Serial Interface Interrupt Status
07h
GL.SIE
Global Ethernet Interface Interrupt Enable
08h
GL.SIS
Global Ethernet Interface Interrupt Status
09h
GL.LIE
Global Serial Interface Interrupt Enable
06h
—
—
—
—
5
0
5
0
5
0
5
0
133 of 335
LIN1TIE
LIN1TIS
—
—
4
0
4
0
4
0
4
0
—
—
—
—
3
0
3
0
3
0
3
0
—
—
—
—
2
0
2
0
2
0
2
0
—
—
—
—
1
0
1
0
1
0
1
0
LIN1RIE
LIN1RIS
SUB1IE
SUB1IS
0
0
0
0
0
0
0
0
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