DS33R41 Maxim Integrated Products, DS33R41 Datasheet - Page 137
DS33R41
Manufacturer Part Number
DS33R41
Description
Network Controller & Processor ICs Inverse-Multiplexing Ethernet Mapper wit
Manufacturer
Maxim Integrated Products
Datasheet
1.DS33R41.pdf
(335 pages)
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Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 7: IMUX Transmit Sync 4 (ITSYNC4). If this bit is set to 1, the device has received a rsync command for the
fourth portion of the 8.192Mbps link from the distant node. This status bit indicates that the distant end is in sync.
Bit 6: IMUX Transmit Sync 3 (ITSYNC3). If this bit is set to 1, the device has received a rsync command for the
third portion of the 8.192Mbps link from the distant node. This status bit indicates that the distant end is in sync.
Bit 5: IMUX Transmit Sync 2 (ITSYNC2). If this bit is set to 1, the device has received a rsync command for the
second portion of the 8.192Mbps link from the distant node. This status bit indicates that the distant end is in sync.
Bit 4: IMUX Transmit Sync 1 (ITSYNC1). If this bit is set to 1, the device has received a rsync command for the
first portion of the 8.192Mbps link from the distant node. This status bit indicates that the distant end is in sync.
Bit 3: IMUX Receive Sync 4 (IRSYNC4). If this bit is set to 1, the local end is in sync for the fourth portion of the
8.192Mbps link. The command states that the local end is in sync.
Bit 2: IMUX Receive Sync 3 (IRSYNC3). If this bit is set to 1, the local end is in sync for the third portion of the
8.192Mbps link. The command states that the local end is in sync.
Bit 1: IMUX Receive Sync 2 (IRSYNC2). If this bit is set to 1, the local end is in sync for the second portion of the
8.192Mbps link. The command states that the local end is in sync.
Bit 0: IMUX Receive Sync 1 (IRSYNC1). If this bit is set to 1, the local end is in sync for the first portion of the
8.192Mbps link. The command states that the local end is in sync.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 7: IMUX Transmit Sync Interrupt Enable 4 (ITSYNCIE4). Setting this bit to 1 enables an interrupt on
ITSYNCLS4.
Bit 6: IMUX Transmit Sync Interrupt Enable 3 (ITSYNCIE3). Setting this bit to 1 enables an interrupt on
ITSYNCLS3.
Bit 5: IMUX Transmit Sync Interrupt Enable 2 (ITSYNCIE2). Setting this bit to 1 enables an interrupt on
ITSYNCLS2.
Bit 4: IMUX Transmit Sync Interrupt Enable 1 (ITSYNCIE1). Setting this bit to 1 enables an interrupt on
ITSYNCLS1.
Bit 3: IMUX Receive Sync Interrupt Enable 4 (IRSYNCIE4). Setting this bit to 1 enables an interrupt on
IRSYNCLS4.
Bit 2: IMUX Receive Sync Interrupt Enable 3 (IRSYNCIE3). Setting this bit to 1 enables an interrupt on
IRSYNCLS3.
Bit 1: IMUX Receive Sync Interrupt Enable 2 (IRSYNCIE2). Setting this bit to 1 enables an interrupt on
IRSYNCLS2.
Bit 0: IMUX Receive Sync Interrupt Enable 1 (IRSYNCIE1). Setting this bit to 1 enables an interrupt on
IRSYNCLS1.
ITSYNC4
ITSYNCIE4
7
0
7
0
ITSYNC3
ITSYNCIE3
6
0
6
0
GL.IMXSS
Inverse MUX Sync Status
18h
GL.IMXSIE
Inverse Mux Sync Interrupt Enable
19h
ITSYNC2
ITSYNCIE2
5
0
5
0
ITSYNC1
ITSYNCIE1
137 of 335
0
0
4
4
IRSYNC4
IRSYNCIE4
3
0
3
0
IRSYNC3
IRSYNCIE3
2
0
2
0
IRSYNC2
IRSYNCIE2
1
0
1
0
IRSYNCIE1
IRSYNC1
0
0
0
0
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