DS33R41 Maxim Integrated Products, DS33R41 Datasheet - Page 135
DS33R41
Manufacturer Part Number
DS33R41
Description
Network Controller & Processor ICs Inverse-Multiplexing Ethernet Mapper wit
Manufacturer
Maxim Integrated Products
Datasheet
1.DS33R41.pdf
(335 pages)
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Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 0: LINE1[0]. This bit is preserved to provide software compatibility with multiport devices. The LINE1[0] bit
selects the Ethernet port that is to be connected to the Serial Interface. Note that bidirectional connection is
assumed between the Serial and Ethernet Interfaces. The connection register and corresponding queue size must
be defined for proper operation. Writing a 0 to this register will disconnect the connection. When a connection is
disconnected, “1”s are sourced to the Serial Interface transmit and to the HDLC receiver and the clocks to the
HDLC transmitter/receiver are disabled.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 3: MAC Read Pointer Reset (C1MRPR). Setting this bit to 1 resets the receive queue read pointer for
connection 1. This queue pointer must be reset after a disconnect and before a connection. The user must clear
the bit before subsequent reset operations.
Bit 2: HDLC Write Pointer Reset (C1HWPR). Setting this bit to 1 resets the receive queue write pointer for
connection 1. This queue pointer must be reset after a disconnect and before a connection. The user must clear
the bit before subsequent reset operations.
Bit 1: HDLC Read Pointer Reset (C1MHPR). Setting this bit to 1 resets the transmit queue read pointer for
connection 1. This queue pointer must be reset after a disconnect and before a connection. The user must clear
the bit before subsequent reset operations.
Bit 0: MAC Transmit Write Pointer Reset (C1HRPR). Setting this bit to 1 resets the transmit queue write pointer
for connection 1. This queue pointer must be reset after a disconnect and before a connection. The user must clear
the bit before subsequent reset operations.
—
—
7
0
7
0
—
—
6
0
6
0
GL.CON1
Connection Register for Ethernet Interface 1
0Eh
GL.C1QPR
Connection 1 Queue Pointer Reset
12h
—
—
5
0
5
0
135 of 335
—
—
0
4
0
4
C1MRPR
—
3
0
3
0
C1HWPR
—
2
0
2
0
C1MHPR
—
1
0
1
0
C1HRPR
LINE1[0]
0
1
0
0
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