DS33R41 Maxim Integrated Products, DS33R41 Datasheet - Page 234

• Manufacturer Part Number: DS33R41
• Description: Network Controller & Processor ICs Inverse-Multiplexing Ethernet Mapper wit
• Manufacturer: Maxim Integrated Products

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 4: Reserved. This bit should be set to 0 for proper operation.
Bit 3: Local Loopback (LLB). When this bit is set to 1, data continues to be transmitted as normal through the
transmit side of the transceiver. Data being received at RTIP and RRING are replaced with the data being
transmitted. Data in this loopback passes through the jitter attenuator. See
Bit 2: Remote Loopback (RLB). When this bit is set to 1, data input by the RPOSI and RNEGI pins is transmitted
back to the TPOSO and TNEGO pins. Data continues to pass through the receive-side framer of the transceiver as
it would normally. Data from the transmit-side formatter is ignored. See Figure 6-3 for more details.
Bit 1: Payload Loopback (PLB). When set to 1, payload loopback is enabled and the following occurs:
1) Data is transmitted from the TPOSO and TNEGO pins synchronous with RCLKn instead of TCLKT.
2) All the receive side signals continue to operate normally.
3) Data at the TSERI and TSIG pins is ignored.
T1 Mode: Normally, this loopback is only enabled when ESF framing is being performed but can also be enabled in
D4 framing applications. The transceiver loops the 192 bits of payload data (with BPVs corrected) from the receive
section back to the transmit section. The FPS framing pattern, CRC6 calculation, and the FDL bits are not looped
back; they are reinserted by the transceiver.
E1 Mode: The transceiver loops the 248 bits of payload data (with BPVs corrected) from the receive section back
to the transmit section. The transmit section modifies the payload as if it was input at TSERI. The FAS word; Si,
Sa, and E bits; and CRC4 are not looped back; they are reinserted by the transceiver.
Bit 0: Framer Loopback (FLB). When this bit is set to 1, the transceiver loops data from the transmit side back to
the receive side. When FLB is enabled, the following occurs:
1) T1 Mode: An unframed all-ones code is transmitted at TPOSO and TNEGO.
2) Data at RPOSI and RNEGI is ignored.
3) All receive-side signals take on timing synchronous with TCLKT instead of RCLKI.
Please note that it is not acceptable to have RCLKn connected to TCLKT during this loopback because this causes
an unstable condition.
E1 Mode: Normal data is transmitted at TPOSO and TNEGO.
—
7
0
TR.LBCR
Loopback Control Register
4Ah
—
6
0
—
5
0
Reserved
234 of 335
4
0
LLB
3
0
Figure 6-3
RLB
2
0
for more details.
PLB
1
0
FLB
0
0