ADSP-21469KBCZ-3 Analog Devices Inc, ADSP-21469KBCZ-3 Datasheet - Page 6

• Manufacturer Part Number: ADSP-21469KBCZ-3
• Description: 400MHz SHARC Processor W/5 Mbits Ram
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: Floating Pointr

Specifications of ADSP-21469KBCZ-3

• Interface: DAI, DPI, EBI/EMI, I²C, SCI, SPI, SSP, UART/USART
• Clock Rate: 400MHz
• Non-volatile Memory: External
• On-chip Ram: 5Mb
• Voltage - I/o: 3.30V
• Voltage - Core: 1.05V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 324-BGA, 324-CSP
• Package: 324CSP-BGA
• Numeric And Arithmetic Format: Floating-Point
• Maximum Speed: 400 MHz
• Ram Size: 640 KB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADSP-21469
floating-point storage format is supported that effectively
doubles the amount of data that may be stored on-chip. Conver-
sion between the 32-bit floating-point and 16-bit floating-point
formats is performed in a single instruction. While each
memory block can store combinations of code and data,
accesses are most efficient when one block stores data using the
DM bus for transfers, and the other block stores instructions
and data using the PM bus for transfers.
Using the DM bus and PM buses, with one bus dedicated to a
memory block, assures single-cycle execution with two data
transfers. In this case, the instruction must be available in the
cache.
The memory map in
address space of the ADSP-21469 processor.
The 48-bit space section describes what this address range looks
like to an instruction that retrieves 48-bit memory. The 32-bit
section describes what this address range looks like to an
instruction that retrieves 32-bit memory.
On-Chip Memory Bandwidth
The internal memory architecture allows programs to have four
accesses at the same time to any of the four blocks (assuming
there are no block conflicts). The total bandwidth is realized
using the DMD and PMD buses (2 × 64-bits, CCLK speed) and
the IOD0/1 buses (2 × 32-bit, PCLK speed).
Table 3. ADSP-21469 Internal Memory Space
IOP Registers 0x0000 0000–0x0003 FFFF
Long Word (64 bits)
BLOCK 0 RAM
0x0004 9000–0x0004 EFFF
Reserved
0x0004 F000–0x0005 8FFF
BLOCK 1 RAM
0x0005 9000–0x0005 EFFF
Reserved
0x0005 F000–0x0005 FFFF
BLOCK 2 RAM
0x0006 0000–0x0006 3FFF
Reserved
0x0006 4000–0x0006 FFFF
BLOCK 3 RAM
0x0007 0000–0x0007 3FFF
Reserved
0x0007 4000–0x0007 FFFF
Table 3
displays the internal memory
Extended Precision Normal or
Instruction Word (48 bits)
BLOCK 0 RAM
0x0008 C000-0x0009 3FFF
Reserved
0x0009 4000–0x0009 5554
BLOCK 1 RAM
0x000A C000-0x000B 3FFF
Reserved
0x000B 4000–0x000B 5554
BLOCK 2 RAM
0x000C 0000–0x000C 5554
Reserved
0x000C 5555–0x000D 5554
BLOCK 3 RAM
0x000E 0000–0x000E 5554
Reserved
0x000E 5555–0x000F 5554
Rev. 0 | Page 6 of 72 | June 2010
Normal Word (32 bits)
BLOCK 0 RAM
0x0009 2000-0x0009 DFFF
Reserved
0x0009 E000–0x000B 1FFF
BLOCK 1 RAM
0x000B 2000-0x000B DFFF
Reserved
0x000B E000–0x000B FFFF
BLOCK 2 RAM
0x000C 0000-0x000C 7FFF
Reserved
0x000C 8000–0x000D FFFF
BLOCK 3 RAM
0x000E 0000–0x000E 7FFF
Reserved
0x000E 8000–0x000F FFFF
Non-Secured ROM
For non-secured ROM, booting modes are selected using the
BOOTCFG pins as shown in
emulation is always enabled, and the IVT is placed on the inter-
nal RAM except for the case where BOOTCFGx = 011.
ROM Based Security
The ADSP-21469 has a ROM security feature that provides
hardware support for securing user software code by preventing
unauthorized reading from the internal code when enabled.
When using this feature, the processor does not boot-load any
external code, executing exclusively from internal ROM. Addi-
tionally, the processor is not freely accessible via the JTAG port.
Instead, a unique 64-bit key, which must be scanned in through
the JTAG or Test Access Port will be assigned to each customer.
The device ignores a wrong key. Emulation features are avail-
able after the correct key is scanned.
Digital Transmission Content Protection
The DTCP specification defines a cryptographic protocol for
protecting audio entertainment content from illegal copying,
intercepting, and tampering as it traverses high performance
digital buses, such as the IEEE 1394 standard. Only legitimate
entertainment content delivered to a source device via another
approved copy protection system (such as the DVD content
scrambling system) is protected by this copy protection system.
Table 8 on Page
BLOCK 0 RAM
0x0012 4000–0x0013 BFFF
Reserved
0x0013 C000–0x0016 3FFF
BLOCK 1 RAM
0x0016 4000-0x0017 BFFF
Reserved
0x0017 C000–0x0017 FFFF
BLOCK 2 RAM
0x0018 0000–0x0018 FFFF
Reserved
0x0019 0000–0x001B FFFF
BLOCK 3 RAM
0x001C 0000–0x001C FFFF
Reserved
0x001D 0000–0x001F FFFF
Short Word (16 bits)
10. In this mode,