ADSP-21469KBCZ-3 Analog Devices Inc, ADSP-21469KBCZ-3 Datasheet
ADSP-21469KBCZ-3
Specifications of ADSP-21469KBCZ-3
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ADSP-21469KBCZ-3 Summary of contents
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... Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies. The ADSP-21469 processor is available with unique audio- centric peripherals such as the digital applications interface, DTCP (digital transmission content protection ...
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... ADSP-21469 TABLE OF CONTENTS Summary ............................................................... 1 Revision History ...................................................... 2 General Description ................................................. 3 Family Core Architecture ........................................ 4 Family Peripheral Architecture ................................ 7 System Design .................................................... 10 Development Tools ............................................. 11 Additional Information ........................................ 11 Related Signal Chains .......................................... 11 Pin Function Descriptions ....................................... 12 Unused DDR2 Pins ............................................. 12 Specifications ........................................................ 17 Operating Conditions .......................................... 17 Electrical Characteristics ....................................... 18 REVISION HISTORY 6/10—Revision 0: Initial Version Absolute Maximum Ratings ................................... 20 ESD Sensitivity ...
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... SHARC family of DSPs that feature Analog Devices’ Super Har- vard Architecture. The processor is source code compatible with the ADSP-2126x, ADSP-2136x, ADSP-2137x, and ADSP-2116x DSPs, as well as with first generation ADSP-2106x SHARC pro- cessors in SISD (single-instruction, single-data) mode. The processor is a 32-bit/40-bit floating point processor optimized ...
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... GFLOPS running at 450 MHz and 2.4 GFLOPS running at 400 MHz. FAMILY CORE ARCHITECTURE The ADSP-21469 is code compatible at the assembly level with the ADSP-2137x, ADSP-2136x, ADSP-2126x, ADSP-21160, and ADSP-21161, and with the first generation ADSP-2106x SHARC processors. The ADSP-21469 shares architectural fea- ...
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... Flexible Instruction Set The 48-bit instruction word accommodates a variety of parallel operations for concise programming. For example, the ADSP-21469 can conditionally execute a multiply, an add, and a subtract in both processing elements while branching and fetch- ing up to four 32-bit values from memory—all in a single instruction ...
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... IVT is placed on the inter- nal RAM except for the case where BOOTCFGx = 011. ROM Based Security The ADSP-21469 has a ROM security feature that provides hardware support for securing user software code by preventing unauthorized reading from the internal code when enabled. ...
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... FAMILY PERIPHERAL ARCHITECTURE The ADSP-21469 family contains a rich set of peripherals that support a wide variety of applications including high quality audio, medical imaging, communications, military, test equip- ment, 3D graphics, speech recognition, motor control, imaging, and other applications. External Port The external port interface supports access to the external mem- ory through core and DMA accesses ...
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... Link ports can operate at a maximum frequency of 166 MHz. MediaLB The ADSP-21469 automotive model has a MLB interface which allows the processor to function as a media local bus device. It includes support for both 3-pin and 5-pin media local bus pro- tocols ...
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... Timers The ADSP-21469 has a total of three timers: a core timer that can generate periodic software interrupts and two general- purpose timers that can generate periodic interrupts and be independently set to operate in one of three modes: ...
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... The following sections provide an introduction to system design options and power supply issues. Program Booting The internal memory of the ADSP-21469 boots at system power-up from an 8-bit EPROM via the external port, link port, an SPI master SPI slave. Booting is determined by the boot configuration (BOOTCFG2–0) pins in Table 8. Boot Mode Selection BOOTCFG2– ...
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... Target Board JTAG Emulator Connector Analog Devices DSP Tools product line of JTAG emulators uses the IEEE 1149.1 JTAG test access port of the ADSP-21469 pro- cessors to monitor and control the target board processor during emulation. Analog Devices DSP Tools product line of JTAG emulators provides emulation at full processor speed, allowing inspection and modification of memory, registers, and processor stacks ...
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... Unused AMI pins can be left unconnected. The MS1 pin can be used in EPORT/FLASH boot mode. For more information, see the ADSP-214xx SHARC Processor Hardware Reference. High-Z AMI Port Read Enable. AMI_RD is asserted whenever the from external memory ...
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... DDR2 On Die Termination. ODT pin when driven high (along with other require- low ments) enables the DDR2 termination resistances. ODT is enabled/disabled regardless of read or write commands. Table asynchronous input output synchronous, A/D = active drive, Rev Page June 2010 ADSP-21469 define which mode registers, 2–0 is driven high. 3-0 line selects the 3-0 ...
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... ADSP-21469 Table 9. Pin Descriptions (Continued) Name Type DAI _P I/O/T (ipu) 20–1 DPI _P I/O/T (ipu) 14–1 LDAT0 I/O/T (ipd) 7–0 LDAT1 7–0 LCLK0 I/O/T (ipd) LCLK1 LACK0 I/O/T (ipd) LACK1 THD_P I THD_M O 1 MLBCLK I (ipd) 1 MLBDAT I/O/T (ipd pin mode. I/T (ipd pin mode ...
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... In this table, the DDR2 pins are SSTL18 compliant. All other pins are LVTTL compliant. 1 The MLB pins are only available on automotive models of the ADSP-21469 processors. These pins are NC (no connect) on the standard models. For more information, see CSP_BGA Ball Assignment—Automotive Models on Page ...
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... ADSP-21469 Table 10. Pin List, Power and Ground Name Type INT EXT THD DDR V P REF GND G AGND G 1 Applies to DDR2 signals. Description Internal Power External Power Analog Power for PLL Thermal Diode Power DDR2 Interface Power DDR2 Input Voltage Reference Ground Analog Ground Rev ...
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... EXT 2.0 1. EXT V REF V + 0.125 REF V REF V + 0.25 REF 0 115 ° C N/A N Rev Page June 2010 ADSP-21469 400 MHz Min Nom Max 1.0 1.05 1.1 3.13 3.3 3.47 1.0 1.05 1.1 1.7 1.8 1.9 3.13 3.3 3.47 0.84 0.9 0.96 2.0 ...
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... Applies to three-statable pins with pull-downs: MLBDAT, MLBSIG, MLBDO, MLBSO, LDAT07-0, LDAT17-0, LCLK0, LCLK1, LACK0, LACK1. 10 Typical internal current data reflects nominal operating conditions. 11 See Engineer-to-Engineer Note “Estimating Power Dissipation for ADSP-2146x SHARC Processors” for further information. 12 Characterized but not tested. 13 Applies to all signal pins ...
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... Operating Conditions on Page 17. Rev Page June 2010 ADSP-21469 Table 13 to calculate this part. The second DD_INT 1 Scaling Factor (ASF) 0.38 0.58 1.23 1.35 2 0.87 0.94 1.00 1 1.10 V 1.15 V ...
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... N/A 366 Operating Conditions on Page 17. PACKAGE INFORMATION may cause perma- The information presented in the package branding for the ADSP-21469 processors. For a complete listing of product availability, see Page Rating –0 +1.15 V –0 +1.9 V Table 15. Package Brand Information –0 +1.9 V –0 +3.6 V Brand Key – ...
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... Note the definitions of the clock periods that are a function of for voltage refer- CLKIN and the appropriate ratio control shown in and Table 16. All of the timing specifications for the ADSP-21469 peripherals are defined in relation to t specific section for each peripheral’s timing information. Table 16. Clock Periods ...
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... ADSP-21469 PLLI CLKIN CLK CLKIN DIVIDER f INPUT XTAL BUF PMCTL (INDIV) DELAY OF 4096 CLKIN CYCLES PLL LOOP PLL VCO FILTER DIVIDER PMCTL (PLLD) PLL MULTIPLIER CLK_CFGx/PMCTL (2xPLLM) CLKOUT (TEST ONLY) BUF Figure 5. Core Clock and System Clock Relationship to CLKIN Rev Page June 2010 ...
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... If setup time is not met, one additional CLKIN cycle may be added to the core reset time, resulting in 4097 t IVDDEVDD t CLKVDD t CLKRST t PLLRST Figure 6. Power-Up Sequencing Rev Page June 2010 ADSP-21469 power supply _ DD INT , a leakage current of the order of three EXT rail has powered up. _ ...
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... Jitter specification is maximum peak-to-peak time interval error (TIE) jitter. CLKIN t CKH Clock Signals The ADSP-21469 can use an external clock or a crystal. See the CLKIN pin description in Table 9. Programs can configure the processor to use its internal clock generator by connecting the necessary components to CLKIN and XTAL. ...
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... Parameter Timing Requirements t Running RESET Pulse Width Low WRUNRST t Running RESET Setup Before CLKIN High SRUNRST CLKIN RUNRSTIN Min 4 × WRST Figure 9. Reset Min 4 × WRUNRST SRUNRST Figure 10. Running Reset Rev Page June 2010 ADSP-21469 Max Unit SRST Max Unit ns ns ...
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... ADSP-21469 Interrupts The following timing specification applies to the FLAG0, FLAG1, and FLAG2 pins when they are configured as IRQ0, IRQ1, and IRQ2 interrupts as well as the DAI_P20–1 and DPI_P14–1 pins when they are configured as interrupts. Table 21. Interrupts Parameter Timing Requirement t IRQx Pulse Width ...
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... TIMER CAPTURE INPUTS Min 2 × t – 1.2 PCLK t PWMO Figure 13. Timer PWM_OUT Timing Min 2 × t PCLK t PWI Figure 14. Timer Width Capture Timing Rev Page June 2010 ADSP-21469 Max Unit 31 2 × (2 – 1) × PCLK Max Unit 31 2 × (2 – 1) × PCLK ...
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... ADSP-21469 Pin to Pin Direct Routing (DAI and DPI) For direct pin connections only (for example DAI_PB01_I to DAI_PB02_O). Table 25. DAI and DPI Pin to Pin Routing Parameter Timing Requirement t Delay DAI/DPI Pin Input Valid to DAI/DPI Output Valid DPIO DAI_Pn DPI_Pn t DPIO DAI_Pm DPI_Pm Figure 15 ...
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... PCG Output Clock Delay After PCG Trigger DTRIGCLK t PCG Frame Sync Delay After PCG Trigger DTRIGFS 1 t Output Clock Period PCGOW D = FSxDIV FSxPHASE. For more information, see the ADSP-214xx SHARC Processor Hardware Reference, “Precision Clock Generators” chapter. 1 Normal mode of operation. DAI_Pn DPI_Pn PCG_TRIGx_I DAI_Pm DPI_Pm ...
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... ADSP-21469 Flags The timing specifications provided below apply to AMI_ADDR23–0 and AMI_DATA7–0 when configured as FLAGS. See Table 9 on Page 12 for more information on flag use. Table 27. Flags Parameter Timing Requirement t DPI_P14–1, AMI_ADDR23–0, AMI_DATA7–0, FLAG3–0 IN Pulse Width FIPW ...
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... DQSCK t RPRE t DQSQ t DQSQ t QH Figure 18. DDR2 SDRAM Controller Input AC Timing Rev Page June 2010 ADSP-21469 1 1 225 MHz Max Min Max 0.7 –1.0 0.7 0.7 –1.0 0.7 0.450 0.450 1.71 0.6 0.25 4.22 2.75 2.05 2.45 2.75 2.05 2.45 1.65 ...
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... ADSP-21469 DDR2 SDRAM Write Cycle Timing Table 29. DDR2 SDRAM Write Cycle Timing, V Parameter Switching Characteristics t Clock Cycle Time CK t Minimum Clock Pulse Width CH t Maximum Clock Pulse Width DQS Latching Rising Transitions to Associated Clock DQSS Edges t Last Data Valid to DQS Delay ...
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... DDR CLK 2_ DDR CLK DDR2_CLK DDR2_CLK , or t SDS. Test Conditions on Page 58 for the calculation of hold times given capacitive and dc loads. , for deassertion of AMI_ACK (low). DSAK Rev Page June 2010 ADSP-21469 Max –5.4 2_ DDR CLK W – 3.2 t –9 DDR CLK W – 7.0 – ...
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... ADSP-21469 AMI_ADDR t DARL AMI_DATA AMI_ACK DRLD t DAD t DSAK t DAAK Figure 20. AMI Read Rev Page June 2010 t DRHA t SDS t HDRH t RWR ...
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... H = (number of hold cycles specified in AMICTLx register) × SDDR CLK , for deassertion of AMI_ACK (low). DSAK t DAWH DDWH t DSAK t DAAK Figure 21. AMI Write Rev Page June 2010 ADSP-21469 Max t – 9 DDR CLK W – 4 DDR CLK ) + H, for the same bank and different banks. DDR2_CLK t DWHA t WWR ...
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... ADSP-21469 Link Ports Calculation of link receiver data setup and hold relative to link clock is required to determine the maximum allowable skew that can be introduced in the transmission path length differ- ence between LDATA and LCLK. Setup skew is the maximum Table 32. Link Ports—Receive Parameter ...
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... LCLK LAST BYTE t LCLKTWL TRANSMITTED specifications apply only to the LACK falling edge. If these specifications are met, HLACH specification. t LCLKTWH . HLACH Figure 23. Link Ports—Transmit Rev Page June 2010 ADSP-21469 Min Max 8 –1 0.5 × t – 0.4 0.6 × 0.4 LCLK LCLK 1 0.4 × ...
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... ADSP-21469 Serial Ports In slave transmitter mode and master receiver mode the maxi- mum serial port frequency is f /8. To determine whether PCLK communication is possible between two devices at clock speed n, the following specifications must be confirmed: 1) frame sync delay and frame sync setup and hold, 2) data delay and data setup and hold, and 3) serial clock (SCLK) width. Table 34. Serial Ports— ...
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... DRIVE EDGE DAI_P20–1 (SCLK) t DFSE t t HFSI HOFSE DAI_P20–1 (FS) t HDTE DAI_P20–1 (DATA CHANNEL A/B) Figure 24. Serial Ports Rev Page June 2010 ADSP-21469 SAMPLE EDGE t SCLKW t t SFSE HFSE t t SDRE HDRE SAMPLE EDGE t SCLKW t t SFSE HFSE ...
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... ADSP-21469 Table 36. Serial Ports—Enable and Three-State Parameter Switching Characteristics 1 t Data Enable from External Transmit SCLK DDTEN 1 t Data Disable from External Transmit SCLK DDTTE 1 t Data Enable from Internal Transmit SCLK DDTIN 1 Referenced to drive edge. DRIVE EDGE DAI_P20–1 (SCLK, EXT) DAI_P20– ...
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... DAI_P20–1 (SCLK, EXT) TDVx DAI_P20-1 t DRDVEN DRIVE EDGE DAI_P20–1 (SCLK, INT) TDVx DAI_P20-1 t DRDVIN Figure 26. Serial Ports—Transmit Data Valid Internal and External Clock Min 3 –0.1 DRIVE EDGE DRIVE EDGE Rev Page June 2010 ADSP-21469 Max Unit DFDVEN t DFDVIN ...
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... ADSP-21469 Table 38. Serial Ports—External Late Frame Sync Parameter Switching Characteristics 1 t Data Delay from Late External Transmit Frame Sync or External DDTLFSE Receive Frame Sync with MCE = 1, MFD = Data Enable for MCE = 1, MFD = 0 DDTENFS 1 The t and t parameters apply to left-justified as well as DSP serial mode, and MCE = 1, MFD = 0. ...
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... DAI_P20–1 (SCLK) DAI_P20–1 (FS) DAI_P20–1 (SDATA) Table 39. IDP Min 3.8 2.5 2.5 2.5 (t PCLK t PCLK t SAMPLE EDGE IPDCLK t IPDCLKW t t SISFS SIHFS t SISD t SIHD Figure 28. IDP Master Timing Rev Page June 2010 ADSP-21469 Max Unit × 4) ÷ 2 – × ...
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... DAI_P20–1 (PDAP_HOLD) DAI_P20–1/ ADDR23–4 (PDAP_DATA) DAI_P20–1 (PDAP_STROBE) PDAP chapter of the ADSP-214xx SHARC Processor Hardware Reference. Note that the 20 bits of external PDAP data can be provided through the AMI_ADDR23–4 pins or over the DAI pins. SAMPLE EDGE t PDCLK t ...
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... CLKIN or any of the DAI pins. DAI_P20–1 (SCLK) DAI_P20–1 (FS) DAI_P20–1 (SDATA) Min 4 5.5 4 5.5 (t × 4) ÷ 2 – 1 PCLK t × 4 PCLK SAMPLE EDGE t SRCCLK t SRCCLKW t t SRCSFS SRCHFS t t SRCSD SRCHD Figure 30. ASRC Serial Input Port Timing Rev Page June 2010 ADSP-21469 Max Unit ...
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... ADSP-21469 Sample Rate Converter—Serial Output Port For the serial output port, the frame sync is an input and it should meet setup and hold times with regard to the serial clock on the output port. The serial data output has a hold time and Table 42. ASRC, Serial Output Port ...
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... PWM Output Pulse Width PWMW t PWM Output Period PWMP PWM OUTPUTS Min t – 2 PCLK 2 × t – 1.5 PCLK t PWMW t PWMP Figure 32. PWM Timing Rev Page June 2010 ADSP-21469 Max Unit 16 (2 – 2) × t – PCLK 16 (2 – 1) × t – 1.5 ns PCLK ...
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... ADSP-21469 S/PDIF Transmitter Serial data input to the S/PDIF transmitter can be formatted as 2 left-justified right-justified with word widths of 16, 18, 20 bits. The following sections provide timing for the transmitter. S/PDIF Transmitter-Serial Input Waveforms Figure 33 shows the right-justified mode. LRCLK is high for the left channel and low for the right channel ...
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... Table 46. S/PDIF Transmitter Left-Justified Mode Parameter Timing Requirement t LRCLK to MSB Delay in Left-Justified Mode LJD DAI_P20–1 LRCLK DAI_P20–1 SCLK DAI_P20–1 SDATA LEFT/RIGHT CHANNEL t LJD MSB MSB–1 MSB–2 LSB+2 LSB+1 Figure 35. Left-Justified Mode Rev Page June 2010 ADSP-21469 Nominal Unit 0 SCLK LSB ...
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... ADSP-21469 S/PDIF Transmitter Input Data Timing The timing requirements for the S/PDIF transmitter are given in Table 47. Input signals are routed to the DAI_P20–1 pins using the SRU. Therefore, the timing specifications provided below are valid at the DAI_P20–1 pins. Table 47. S/PDIF Transmitter Input Data Timing ...
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... Serial clock frequency is 64 × Frame Sync, where FS = the frequency of LRCLK. DAI_P20–1 (SCLK) DAI_P20–1 (FS) DAI_P20–1 (DATA CHANNEL A/B) DRIVE EDGE t SCLKIW t DFSI t HOFSI t DDTI t HDTI Figure 37. S/PDIF Receiver Internal Digital PLL Mode Timing Rev Page June 2010 ADSP-21469 Min Max 5 –2 5 –2 8 × t – 2 PCLK SAMPLE EDGE Unit ...
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... ADSP-21469 SPI Interface—Master The ADSP-21469 contains two SPI ports. Both primary and sec- ondary are available through DPI only. The timing provided in Table 50 and Table 51 applies to both. Table 50. SPI Interface Protocol—Master Switching and Timing Specifications Parameter Timing Requirements t Data Input Valid to SPICLK Edge (Data Input Setup Time) ...
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... CPHASE = 1 SSPIDS MOSI (INPUT) MISO (OUTPUT) t DSOV CPHASE = 0 MOSI (INPUT) t SPICLS t DDSPIDS t DDSPIDS t SSPIDS Figure 39. SPI Slave Timing Rev Page June 2010 ADSP-21469 Min Max 4 × t – 2 PCLK 2 × t – 2 PCLK 2 × t – 2 PCLK 2 × t PCLK 2 × t PCLK × t PCLK 0 6.8 ...
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... ADSP-21469 Media Local Bus All the numbers given are applicable for all speed modes (1024 Fs, 512 Fs, and 256 Fs for 3-pin; 512 Fs and 256 Fs for 5- pin) unless otherwise specified. Please refer to MediaLB specifi- cation document rev 3.0 for more details. Table 52. MLB Interface, 3-Pin Specifications ...
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... MediaLB signal lines when not being driven. VALID t DHMCF t DSMCF t MLBCLK t t MCKH t t MCKR MCKF t t MCDRV MCFDZ VALID Figure 40. MLB Timing (3-Pin Interface) Min Rev Page June 2010 ADSP-21469 MCKL t MDZH Typ Max Unit p ...
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... ADSP-21469 MLBSIG, MLBDAT (Rx, Input) MLBCLK MLBSO, MLBDO (Tx, Output) VALID t DHMCF t DSMCF t MLBCLK t t MCKH t t MCKR MCKF t MCDRV VALID Figure 41. MLB Timing (5-Pin Interface) MLBCLK t MPWV Figure 42. MLB 3-Pin and 5-Pin MLBCLK Pulse Width Variation Timing Rev Page June 2010 MCKL ...
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... Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing For information on the UART port receive and transmit opera- tions, see the ADSP-214xx SHARC Hardware Reference Manual. 2-Wire Interface (TWI)—Receive and Transmit Timing For information on the TWI receive and transmit operations, see the ADSP-214xx SHARC Hardware Reference Manual ...
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... MEAS OUTPUT Figure 45. Voltage Reference Levels for AC Measurements OUTPUT DRIVE CURRENTS Figure 46 57. These include output drivers of the ADSP-21469, and associated with each driver. The curves represent the current drive capability of the output drivers as a function of output voltage. level MEAS Table 55. Driver Types ...
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... Figure 57 may not 0.8 0.7 0.6 0.5 0.4 TYPE A DRIVE RISE 0 0.0342x + 0.309 0.2 TYPE B DRIVE RISE 0 0.0153x + 0.2131 125 150 175 200 Rev Page June 2010 ADSP-21469 100 125 LOAD CAPACITANCE (pF) Figure 49. Typical Output Rise/Fall Time Non-DDR2 (20 Min) DD_EXT TYPE C & ...
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... ADSP-21469 4 3.5 TYPE C & D HALF DRIVE FALL y = 0.0841x + 0.8997 3 2.5 2 1.5 TYPE C & D FULL DRIVE RISE y = 0.0304x + 0.8204 1 0 LOAD CAPACITANCE (pF) Figure 51. Typical Output Rise/Fall Time DDR2 (20 Min) DD_EXT 10 9 TYPE A DRIVE FALL 0.0359x + 2.9227 TYPE B DRIVE FALL 0.0136x + 3.1135 ...
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... THERMAL CHARACTERISTICS The ADSP-21469 processor is rated for performance over the temperature range specified in Page 17. Table 56 airflow measurements comply with JEDEC standards JESD51-2 and JESD51-6, and the junction-to-board measure- ment complies with JESD51-8. Test board design complies with JEDEC standards JESD51-7 (CSP_BGA). The junction-to-case measurement complies with MIL- STD-883 ...
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... Airflow = 2 m/s 0.24 JMT Thermal Diode The ADSP-21469 processors incorporate thermal diodes to monitor the die temperature. The thermal diode grounded collector PNP bipolar junction transistor (BJT). The THD_P pin is connected to the emitter and the THD_M pin is connected to the base of the transistor. These pins can be used by an external temperature sensor (such as ADM 1021A or LM86, or others) to read the die temperature of the chip ...
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... C16 DDR2_WE B16 DPI_P01 A16 DPI_P02 B17 DPI_P03 A17 DPI_P04 C18 DPI_P05 C17 DPI_P06 B18 DPI_P07 C07 DPI_P08 Rev Page June 2010 ADSP-21469 Ball No. Signal Ball No. E01 DPI_P09 N01 A07 DPI_P10 N02 B07 DPI_P11 N03 A13 DPI_P12 N04 B13 DPI_P13 M03 ...
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... ADSP-21469 Table 58. CSP_BGA Ball Assignment (Alphabetical by Signal) (Continued) Signal Ball No. Signal GND H07 GND GND H08 GND GND H09 LACK_0 GND H10 LACK_1 GND H11 LCLK_0 GND H12 LCLK_1 GND J01 LDAT0_0 GND J07 LDAT0_1 GND J08 LDAT0_2 GND J09 LDAT0_3 ...
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... A1 CORNER INDEX AREA DD_INT V DD_EXT GND I/O SIGNALS Figure 58. Ball Configuration, Automotive Model Rev Page June 2010 DD_DDR2 V REF DD_THD V A DD_A S AGND ADSP-21469 ...
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... ADSP-21469 CSP_BGA BALL ASSIGNMENT—STANDARD MODELS Table 59 lists the standard model CSP_BGA ball assignments by signal. Table 59. CSP_BGA Ball Assignment (Alphabetical by Signal) Signal Ball No. Signal AGND H02 CLK_CFG1 AMI_ACK R10 CLKIN AMI_ADDR0 V16 DAI_P01 AMI_ADDR01 U16 DAI_P02 AMI_ADDR02 T16 DAI_P03 AMI_ADDR03 R16 ...
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... DD INT D03 INT D06 INT D08 INT D18 INT E02 INT Rev Page June 2010 ADSP-21469 Ball No. Signal Ball No. E04 V F13 _ DD INT E07 V G06 _ DD INT E10 V G13 _ DD INT E11 V H05 _ DD INT E17 V H06 _ DD INT F03 ...
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... ADSP-21469 A1 CORNER INDEX AREA DD_INT DD_DDR2 V REF V R DD_EXT V DD_THD T GND DD_A S AGND I/O SIGNALS Figure 59. Ball Configuration, Standard Model Rev Page June 2010 ...
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... OUTLINE DIMENSIONS The ADSP-21469 processor is available CSP_BGA lead-free package. A1 BALL CORNER * 1.80 1.71 1.56 Figure 60. 324-Ball Chip Scale Package, Ball Grid Array [CSP_BGA] SURFACE-MOUNT DESIGN The following table is provided as an aid to PCB design. For industry-standard design recommendations, refer to IPC-7351, Generic Requirements for Surface-Mount Design and Land Pat- tern Standard ...
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... ORDERING GUIDE Temperature 1 2 Model Range ADSP-21469KBCZ-3 0C to +70C ADSP-21469BBCZ-3 –40C to +85C ADSP-21469KBCZ-4 0C to +70 RoHS compliant part. 2 Referenced temperature is ambient temperature. The ambient temperature is not a specification. Please see specification, which is the only temperature specification ...
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... Rev Page June 2010 ADSP-21469 ...
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... ADSP-21469 ©2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07900-0-6/10(0) Rev Page June 2010 ...