ADSP-21469KBCZ-3 Analog Devices Inc, ADSP-21469KBCZ-3 Datasheet - Page 5

• Manufacturer Part Number: ADSP-21469KBCZ-3
• Description: 400MHz SHARC Processor W/5 Mbits Ram
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: Floating Pointr

Specifications of ADSP-21469KBCZ-3

• Interface: DAI, DPI, EBI/EMI, I²C, SCI, SPI, SSP, UART/USART
• Clock Rate: 400MHz
• Non-volatile Memory: External
• On-chip Ram: 5Mb
• Voltage - I/o: 3.30V
• Voltage - Core: 1.05V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 324-BGA, 324-CSP
• Package: 324CSP-BGA
• Numeric And Arithmetic Format: Floating-Point
• Maximum Speed: 400 MHz
• Ram Size: 640 KB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

other data structures required in digital signal processing, and
are commonly used in digital filters and Fourier transforms.
The two DAGs of the processors contain sufficient registers to
allow the creation of up to 32 circular buffers (16 primary regis-
ter sets, 16 secondary). The DAGs automatically handle address
pointer wraparound, reduce overhead, increase performance,
and simplify implementation. Circular buffers can start and end
at any memory location.
Flexible Instruction Set
The 48-bit instruction word accommodates a variety of parallel
operations for concise programming. For example, the
ADSP-21469 can conditionally execute a multiply, an add, and a
subtract in both processing elements while branching and fetch-
ing up to four 32-bit values from memory—all in a single
instruction.
Variable Instruction Set Architecture (VISA)
In addition to supporting the standard 48-bit instructions from
previous SHARC processors, the ADSP-21469 supports new
instructions of 16 and 32 bits. This feature, called Variable
80-BIT
MRF
SIMD Core
MULTIPLIER
DAG1
16x32
DMD/PMD 64
80-BIT
MRB
SHIFTER
DAG2
16x32
ALU
Figure 2. SHARC Core Block Diagram
JTAG
Rev. 0 | Page 5 of 72 | June 2010
16x40-BIT
ASTATx
STYKx
Rx/Fx
PEx
RF
FLAG
PROGRAM SEQUENCER
TIMER
5 STAGE
DATA
SWAP
INTERRUPT
16x40-BIT
Instruction Set Architecture (VISA), drops redundant/unused
bits within the 48-bit instruction to create more efficient and
compact code. The program sequencer supports fetching these
16-bit and 32-bit instructions from both internal and external
DDR2 memory. Source modules need to be built using the
VISA option in order to allow code generation tools to create
these more efficient opcodes.
On-Chip Memory
The processors contain 5 Mbits of internal RAM. Each block
can be configured for different combinations of code and data
storage (see
independent accesses by the core processor and I/O processor.
The ADSP-21469 memory architecture, in combination with its
separate on-chip buses, allows two data transfers from the core
and one from the I/O processor in a single cycle.
The processor’s SRAM can be configured as a maximum of
160k words of 32-bit data, 320k words of 16-bit data, 106.7k
words of 48-bit instructions (or 40-bit data), or combinations of
different word sizes up to 5 Mbits. All of the memory can be
accessed as 16-bit, 32-bit, 48-bit, or 64-bit words. A 16-bit
ASTATy
Sx/SFx
STYKy
PEy
RF
CACHE
PM ADDRESS 32
DM ADDRESS 32
Table
PM DATA 64
DM DATA 64
ALU
4). Each memory block supports single-cycle,
PM ADDRESS 24
PM DATA 48
SHIFTER
80-BIT
MSB
MULTIPLIER
4x32-BIT
SYSTEM
USTAT
64-BIT
PX
I/F
80-BIT
MSF
ADSP-21469