ADSP-21469KBCZ-3 Analog Devices Inc, ADSP-21469KBCZ-3 Datasheet - Page 38

• Manufacturer Part Number: ADSP-21469KBCZ-3
• Description: 400MHz SHARC Processor W/5 Mbits Ram
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: Floating Pointr

Specifications of ADSP-21469KBCZ-3

• Interface: DAI, DPI, EBI/EMI, I²C, SCI, SPI, SSP, UART/USART
• Clock Rate: 400MHz
• Non-volatile Memory: External
• On-chip Ram: 5Mb
• Voltage - I/o: 3.30V
• Voltage - Core: 1.05V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 324-BGA, 324-CSP
• Package: 324CSP-BGA
• Numeric And Arithmetic Format: Floating-Point
• Maximum Speed: 400 MHz
• Ram Size: 640 KB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADSP-21469
Serial Ports
In slave transmitter mode and master receiver mode the maxi-
mum serial port frequency is f
communication is possible between two devices at clock speed
n, the following specifications must be confirmed: 1) frame sync
delay and frame sync setup and hold, 2) data delay and data
setup and hold, and 3) serial clock (SCLK) width.
Table 34. Serial Ports—External Clock
1
2
Table 35. Serial Ports—Internal Clock
1
2
Parameter
Timing Requirements
t
t
t
t
t
t
Switching Characteristics
t
t
t
t
Parameter
Timing Requirements
t
t
t
t
Switching Characteristics
t
t
t
t
t
t
t
Referenced to sample edge.
Referenced to drive edge.
Referenced to the sample edge.
Referenced to drive edge.
SFSE
HFSE
SDRE
HDRE
SCLKW
SCLK
DFSE
HOFSE
DDTE
HDTE
SFSI
HFSI
SDRI
HDRI
DFSI
HOFSI
DFSIR
HOFSIR
DDTI
HDTI
SCLKIW
1
1
2
1
1
1
2
1
2
2
1
1
2
2
2
2
2
2
Frame Sync Setup Before SCLK
(Externally Generated Frame Sync in either Transmit or Receive Mode)
Frame Sync Hold After SCLK
(Externally Generated Frame Sync in either Transmit or Receive Mode)
Receive Data Setup Before SCLK
Receive Data Hold After SCLK
Frame Sync Delay After SCLK (Internally Generated Frame Sync in Transmit Mode)
Frame Sync Hold After SCLK (Internally Generated Frame Sync in Transmit Mode) –1.0
Frame Sync Delay After SCLK (Internally Generated Frame Sync in Receive Mode)
Frame Sync Hold After SCLK (Internally Generated Frame Sync in Receive Mode)
Transmit Data Delay After SCLK
Transmit Data Hold After SCLK
Transmit or Receive SCLK Width
Frame Sync Setup Before SCLK
(Externally Generated Frame Sync in either Transmit or Receive Mode)
Frame Sync Hold After SCLK
(Externally Generated Frame Sync in either Transmit or Receive Mode)
Receive Data Setup Before Receive SCLK
Receive Data Hold After SCLK
SCLK Width
SCLK Period
Frame Sync Delay After SCLK
(Internally Generated Frame Sync in either Transmit or Receive Mode)
Frame Sync Hold After SCLK
(Internally Generated Frame Sync in either Transmit or Receive Mode)
Transmit Data Delay After Transmit SCLK
Transmit Data Hold After Transmit SCLK
PCLK
/8. To determine whether
Rev. 0 | Page 38 of 72 | June 2010
Serial port signals are routed to the DAI_P20–1 pins using the
SRU. Therefore, the timing specifications provided below are
valid at the DAI_P20–1 pins. In
or the falling edge of SCLK (external or internal) can be used as
the active sampling edge.
Min
2.5
2.5
1.9
2.5
(t
t
2
2
Min
7
2.5
7
2.5
–1.0
–1.25
2 × t
PCLK
PCLK
× 4
PCLK
× 4) ÷ 2 – 0.5
– 1.5
Figure 24
Max
4
9.75
3.25
2 × t
Max
10.25
8.5
PCLK
either the rising edge
+ 1.5
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns