ADSP-21469KBCZ-3 Analog Devices Inc, ADSP-21469KBCZ-3 Datasheet - Page 3

• Manufacturer Part Number: ADSP-21469KBCZ-3
• Description: 400MHz SHARC Processor W/5 Mbits Ram
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: Floating Pointr

Specifications of ADSP-21469KBCZ-3

• Interface: DAI, DPI, EBI/EMI, I²C, SCI, SPI, SSP, UART/USART
• Clock Rate: 400MHz
• Non-volatile Memory: External
• On-chip Ram: 5Mb
• Voltage - I/o: 3.30V
• Voltage - Core: 1.05V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 324-BGA, 324-CSP
• Package: 324CSP-BGA
• Numeric And Arithmetic Format: Floating-Point
• Maximum Speed: 400 MHz
• Ram Size: 640 KB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

GENERAL DESCRIPTION
The ADSP-21469 SHARC
SHARC family of DSPs that feature Analog Devices’ Super Har-
vard Architecture. The processor is source code compatible with
the ADSP-2126x, ADSP-2136x, ADSP-2137x, and ADSP-2116x
DSPs, as well as with first generation ADSP-2106x SHARC pro-
cessors in SISD (single-instruction, single-data) mode. The
processor is a 32-bit/40-bit floating point processor optimized
for high performance audio applications with its large on-chip
SRAM, multiple internal buses to eliminate I/O bottlenecks, and
an innovative digital applications interface (DAI).
Table 1
processor, and
Table 1. Processor Benchmarks
1
Table 2. SHARC Family Features
Benchmark Algorithm
1024 Point Complex FFT (Radix 4, with Reversal) 20.44 s
FIR Filter (Per Tap)
IIR Filter (Per Biquad)
Matrix Multiply (Pipelined)
[3 × 3] × [3 × 1]
[4 × 4] × [4 × 1]
Divide (y/x)
Inverse Square Root
Assumes two files in multichannel SIMD mode
Feature
Maximum Frequency
RAM
ROM
Audio Decoders in ROM
DTCP Hardware Accelerator
Pulse-Width Modulation
S/PDIF
DDR2 Memory Interface
DDR2 Memory Bus Width
Direct DMA from SPORTs to
External Memory
FIR, IIR, FFT Accelerator
MLB Interface
IDP
Serial Ports
DAI (SRU)/DPI (SRU2)
shows performance benchmarks for the ADSP-21469
Table 2
1
1
shows the product’s features.
1
®
processor is a member of the SIMD
2
Automotive Models Only
ADSP-21469
20/14 pins
450 MHz
5M Bits
16 Bits
N/A
Yes
Yes
Yes
Yes
Yes
Yes
No
No
Speed
(at 450 MHz)
1.11 ns
4.43 ns
10.0 ns
17.78 ns
6.67 ns
10.0 ns
8
Rev. 0 | Page 3 of 72 | June 2010
Table 2. SHARC Family Features (Continued)
1
2
Figure 1 on Page 1
the ADSP-21469 processors. The core clock domain contains
the following features:
Figure 1 on Page 1
known as the I/O processor) which contains the following
features:
Audio decoding algorithms include PCM, Dolby Digital EX, Dolby Pro Logic IIx,
These products contain the Digital Transmission Content Protection protocol, a
Feature
UART
Link Ports
AMI Interface with 8-bit Support
SPI
TWI
SRC Performance
Package
DTS 96/24, Neo:6, DTS ES, MPEG-2 AAC, MP3, and functions like bass
management, delay, speaker equalization, graphic equalization, and more.
Decoder/postprocessor algorithm combination support varies depending upon
the chip version and the system configurations. Please visit www.analog.com for
complete product information and availability.
proprietary security protocol. Contact your Analog Devices sales office for more
information.
• Two processing elements (PEx, PEy), each of which com-
• Data address generators (DAG1, DAG2)
• Program sequencer with instruction cache
• One periodic interval timer with pinout
• PM and DM buses capable of supporting 2 × 64-bit data
• On-chip SRAM (5M bit)
• On-chip mask-programmable ROM (4M bit)
• JTAG test access port for emulation and boundary scan.
• IOD0 (peripheral DMA) and IOD1 (external port DMA)
• Peripheral and external port buses for core connection
• External port with an AMI and DDR2 controller
• 4 units for PWM control
• 1 MTM unit for internal-to-internal memory transfers
prises an ALU, multiplier, shifter, and data register file
transfers between memory and the core at every core pro-
cessor cycle
The JTAG provides software debug through user break-
points which allows flexible exception handling.
buses for 32-bit data transfers
also shows the peripheral clock domain (also
shows the two clock domains that make up
324-ball CSP_BGA
ADSP-21469
ADSP-21469
–128 dB
Yes
Yes
1
2
2