ADSP-21469KBCZ-3 Analog Devices Inc, ADSP-21469KBCZ-3 Datasheet - Page 12

• Manufacturer Part Number: ADSP-21469KBCZ-3
• Description: 400MHz SHARC Processor W/5 Mbits Ram
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: Floating Pointr

Specifications of ADSP-21469KBCZ-3

• Interface: DAI, DPI, EBI/EMI, I²C, SCI, SPI, SSP, UART/USART
• Clock Rate: 400MHz
• Non-volatile Memory: External
• On-chip Ram: 5Mb
• Voltage - I/o: 3.30V
• Voltage - Core: 1.05V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 324-BGA, 324-CSP
• Package: 324CSP-BGA
• Numeric And Arithmetic Format: Floating-Point
• Maximum Speed: 400 MHz
• Ram Size: 640 KB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADSP-21469
PIN FUNCTION DESCRIPTIONS
UNUSED DDR2 PINS
When the DDR2 controller is not used:
Table 9. Pin Descriptions
Name
AMI_ADDR
AMI_DATA
AMI_ACK
AMI_MS
AMI_RD
AMI_WR
FLAG[0]/IRQ0
FLAG[1]/IRQ1
FLAG[2]/IRQ2/
AMI_MS2
FLAG[3]/TMREXP/
AMI_MS3
The following symbols appear in the Type column of
O/D = open-drain, and T = three-state, ipd = internal pull-down resistor, ipu = internal pull-up resistor.
The internal pull-up (ipu) and internal pull-down (ipd) resistors are designed to hold the internal path from the pins at the expected logic levels.
To pull-up or pull-down the external pads to the expected logic levels, use external resistors. Internal pull-up/pull-down resistors cannot be
enabled/disabled and the value of these resistors cannot be programmed. The range of an ipu resistor can be between 26 k–63 k. The range
of an ipd resistor can be between 31 k–85 k.
In this table, the DDR2 pins are SSTL18 compliant. All other pins are LVTTL compliant.
• Leave the DDR2 signal pins floating.
• Internally, three-state the DDR2 I/O signals. This can be
done by setting the DIS_DDRCTL bit of DDR2CTL0
register.
0–1
7–0
23–0
Type
I/O/T (ipu)
I/O/T (ipu)
I (ipu)
O/T (ipu)
O/T (ipu)
O/T (ipu)
I/O (ipu)
I/O (ipu)
I/O (ipu)
I/O (ipu)
State During/
After Reset
low (boot)
High-Z
High-Z
High-Z
High-Z
FLAG[0] INPUT
FLAG[1] INPUT
FLAG[2] INPUT
FLAG[3] INPUT
High-Z/driven
Rev. 0 | Page 12 of 72 | June 2010
Table
Description
External Address. The
peripherals on these pins. The data pins can be multiplexed to support the PDAP (I)
and PWM (O). After reset, all AMI_ADDR
mode and FLAG(0–3) pins are in FLAGS mode (default). When configured in the
IDP_PDAP_CTL register, IDP channel 0 scans the AMI_ADDR
data. Unused AMI pins can be left unconnected.
External Data. The data pins can be multiplexed to support the external memory
interface data (I/O), the PDAP (I), FLAGS (I/O) and PWM (O). After reset, all AMI_DATA
pins are in EMIF mode and FLAG(0-3) pins are in FLAGS mode (default). Unused AMI
pins can be left unconnected.
Memory Acknowledge (AMI_ACK). External devices can deassert AMI_ACK (low) to
add wait states to an external memory access. AMI_ACK is used by I/O devices,
memory controllers, or other peripherals to hold off completion of an external
memory access. Unused AMI pins can be left unconnected.
Memory Select Lines 0–1. These lines are asserted (low) as chip selects for the corre-
sponding banks of external memory on the AMI interface. The MS
decoded memory address lines that change at the same time as the other address
lines. When no external memory access is occurring the MS
are active however when a conditional memory access instruction is executed,
whether or not the condition is true. Unused AMI pins can be left unconnected.
The MS1 pin can be used in EPORT/FLASH boot mode. For more information, see the
ADSP-214xx SHARC Processor Hardware Reference.
AMI Port Read Enable. AMI_RD is asserted whenever the
from external memory.
External Port Write Enable. AMI_WR is asserted when the processor writes a word
to external memory.
FLAG0/Interrupt Request0.
FLAG1/Interrupt Request1.
FLAG2/Interrupt Request2/Async Memory Select2.
FLAG3/Timer Expired/Async Memory Select3.
9: A = asynchronous, I = input, O = output, S = synchronous, A/D = active drive,
• Power down the receive path by setting the PWD bits of the
• Connect the V
• Leave V
DDR2PADCTLx register.
processor
REF
floating/unconnected.
outputs addresses for external memory and
DD_DDR2
23–0
pins are in external memory interface
pins to the V
DD_INT
1-0
processor
23–0
lines are inactive; they
pins for parallel input
supply.
1-0
lines are
reads a word