ADSP-21469KBCZ-3 Analog Devices Inc, ADSP-21469KBCZ-3 Datasheet - Page 23

• Manufacturer Part Number: ADSP-21469KBCZ-3
• Description: 400MHz SHARC Processor W/5 Mbits Ram
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: Floating Pointr

Specifications of ADSP-21469KBCZ-3

• Interface: DAI, DPI, EBI/EMI, I²C, SCI, SPI, SSP, UART/USART
• Clock Rate: 400MHz
• Non-volatile Memory: External
• On-chip Ram: 5Mb
• Voltage - I/o: 3.30V
• Voltage - Core: 1.05V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 324-BGA, 324-CSP
• Package: 324CSP-BGA
• Numeric And Arithmetic Format: Floating-Point
• Maximum Speed: 400 MHz
• Ram Size: 640 KB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Power-Up Sequencing
The timing requirements for processor startup are given in
Table
between V
ations that the system designs should take into account.
Table 17. Power Up Sequencing Timing Requirements (Processor Startup)
1
2
3
4
5
Parameter
Timing Requirements
t
t
t
t
t
t
Switching Characteristic
t
Valid V
Assumes a stable CLKIN signal, after meeting worst-case startup timing of crystal oscillators. Refer to your crystal oscillator manufacturer's data sheet for startup time. Assume
Based on CLKIN cycles.
Applies after the power-up sequence is complete. Subsequent resets require a minimum of four CLKIN cycles for RESET to be held low in order to properly initialize and
The 4096 cycle count depends on t
RSTVDD
IVDD
EVDD
CLKVDD
CLKRST
PLLRST
CORERST
design of the power supply subsystem.
a 25 ms maximum oscillator startup time if using the XTAL pin and internal oscillator circuit in conjunction with an external crystal.
propagate default states at all I/O pins.
cycles maximum.
• No power supply should be powered up for an extended
• If V
-
period of time (> 200 ms) before another supply starts to
ramp up.
such as RESETOUT and RESET, may actually drive
momentarily until the V
_
EVDD
DDR
17. While no specific power-up sequencing is required
1
DD
2
DD
_
VDD
INT
DD
_
INT
assumes that the supply is fully ramped to its nominal value. Voltage ramp rates can vary from microseconds to hundreds of milliseconds depending on the
_
EXT
power supply comes up after V
, V
CLK_CFG1–0
RESETOUT
RESET
V
DD
V
CLKIN
DDINT
DDEXT
_
DDR
RESET Low Before V
V
V
CLKIN Valid After V
CLKIN Valid Before RESET Deasserted
PLL Control Setup Before RESET Deasserted
Core Reset Deasserted After RESET Deasserted
2
, and V
DD
DD
_
_
INT
EXT
SRST
DD
On Before V
On Before V
_
INT
specification in
DD
rail has powered up. Systems
_
INT
t
RSTVDD
, there are some consider-
DD
DD
DD
DD
_
_
_
Table
EXT
DDR
_
INT
DD
INT
t
_
2
or V
IVDDEVDD
EXT
or V
19. If setup time is not met, one additional CLKIN cycle may be added to the core reset time, resulting in 4097
, any pin,
DD
Rev. 0 | Page 23 of 72 | June 2010
DD
_
_
EXT
Figure 6. Power-Up Sequencing
EXT
or V
or V
t
CLKVDD
DD
DD
_
_
DDR
DDR
t
PLLRST
2
2
Valid
On
t
CLKRST
Note that during power-up, when the V
comes up after V
state leakage current pull-up, pull-down may be observed on
any pin, even if that pin is an input only (for example the RESET
pin) until the V
sharing these signals on the board must determine if there
are any issues that need to be addressed based on this
behavior.
DD
Min
0
–200
–200
0
10
20
4096 × t
DD
_
t
INT
2
3
CORERST
_
EXT
rail has powered up.
, a leakage current of the order of three-
CK
+ 2 × t
CCLK
4, 5
DD
_
INT
ADSP-21469
Max
+200
+200
200
power supply
Unit
ms
ms
ms
ms
ms
ms
ms