ADSP-21469KBCZ-3 Analog Devices Inc, ADSP-21469KBCZ-3 Datasheet - Page 36

• Manufacturer Part Number: ADSP-21469KBCZ-3
• Description: 400MHz SHARC Processor W/5 Mbits Ram
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: Floating Pointr

Specifications of ADSP-21469KBCZ-3

• Interface: DAI, DPI, EBI/EMI, I²C, SCI, SPI, SSP, UART/USART
• Clock Rate: 400MHz
• Non-volatile Memory: External
• On-chip Ram: 5Mb
• Voltage - I/o: 3.30V
• Voltage - Core: 1.05V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 324-BGA, 324-CSP
• Package: 324CSP-BGA
• Numeric And Arithmetic Format: Floating-Point
• Maximum Speed: 400 MHz
• Ram Size: 640 KB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADSP-21469
Link Ports
Calculation of link receiver data setup and hold relative to link
clock is required to determine the maximum allowable skew
that can be introduced in the transmission path length differ-
ence between LDATA and LCLK. Setup skew is the maximum
Table 32. Link Ports—Receive
1
Parameter
Timing Requirements
t
t
t
t
t
Switching Characteristics
t
LACK goes low with t
SLDCL
HLDCL
LCLKIW
LCLKRWL
LCLKRWH
DLALC
LACK (OUT)
LDAT7–0
LCLK
Data Setup Before LCLK Low
Data Hold After LCLK Low
LCLK Period
LCLK Width Low
LCLK Width High
LACK Low Delay After LCLK Low
DLALC
relative to rise of LCLK after first byte, but does not go low if the receiver's link buffer is not about to fill.
t
LCLKRWH
1
Rev. 0 | Page 36 of 72 | June 2010
t
SLDCL
Figure 22. Link Ports—Receive
IN
t
LCLKIW
delay that can be introduced in LDATA relative to LCLK:
(setup skew = t
the maximum delay that can be introduced in LCLK relative to
LDATA: (hold skew = t
t
HLDCL
t
LCLKRWL
t
Min
0.5
1.5
t
2.6
2.6
5
DLALC
LCLK
LCLKTWH
(6 ns)
LCLKTWL
min – t
DLDCH
Max
12
min – t
– t
HLDCH
SLDCL
). Hold skew is
– t
HLDCL
Unit
ns
ns
ns
ns
ns
ns
).