ADSP-21469KBCZ-3 Analog Devices Inc, ADSP-21469KBCZ-3 Datasheet - Page 13

• Manufacturer Part Number: ADSP-21469KBCZ-3
• Description: 400MHz SHARC Processor W/5 Mbits Ram
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: Floating Pointr

Specifications of ADSP-21469KBCZ-3

• Interface: DAI, DPI, EBI/EMI, I²C, SCI, SPI, SSP, UART/USART
• Clock Rate: 400MHz
• Non-volatile Memory: External
• On-chip Ram: 5Mb
• Voltage - I/o: 3.30V
• Voltage - Core: 1.05V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 324-BGA, 324-CSP
• Package: 324CSP-BGA
• Numeric And Arithmetic Format: Floating-Point
• Maximum Speed: 400 MHz
• Ram Size: 640 KB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 9. Pin Descriptions (Continued)
Name
DDR2_ADDR
DDR2_BA
DDR2_CAS
DDR2_CKE
DDR2_CS
DDR2_DATA
DDR2_DM
DDR2_DQS
DDR2_DQS
DDR2_RAS
DDR2_WE
DDR2_CLK0,
DDR2_CLK0,
DDR2_CLK1,
DDR2_CLK1
DDR2_ODT
The following symbols appear in the Type column of
O/D = open-drain, and T = three-state, ipd = internal pull-down resistor, ipu = internal pull-up resistor.
The internal pull-up (ipu) and internal pull-down (ipd) resistors are designed to hold the internal path from the pins at the expected logic levels.
To pull-up or pull-down the external pads to the expected logic levels, use external resistors. Internal pull-up/pull-down resistors cannot be
enabled/disabled and the value of these resistors cannot be programmed. The range of an ipu resistor can be between 26 k–63 k. The range
of an ipd resistor can be between 31 k–85 k.
In this table, the DDR2 pins are SSTL18 compliant. All other pins are LVTTL compliant.
3-0
2-0
1-0
1-0
1-0
15-0
15–0
Type
O/T
O/T
O/T
O/T
O/T
I/O/T
O/T
I/O/T (Differential)
O/T
O/T
O/T (Differential)
O/T
State During/
After Reset
High-Z/driven
low
High-Z/driven
low
High-Z/driven
high
High-Z/driven
low
High-Z/driven
high
High-Z
High-Z/driven
high
High-Z
High-Z/driven
high
High-Z/driven
high
High-Z/driven
low
High-Z/driven
low
Rev. 0 | Page 13 of 72 | June 2010
Table
Description
DDR2 Address. DDR2 address pins.
DDR2 Bank Address Input. Defines which internal bank an ACTIVATE, READ, WRITE,
or PRECHARGE command is being applied to. BA
including MR, EMR, EMR(2), and EMR(3) are loaded during the LOAD MODE REGISTER
command.
DDR2 Column Address Strobe. Connect to DDR2_CAS pin; in conjunction with
other DDR2 command pins, defines the operation for the DDR2 to perform.
DDR2 Clock Enable Output to DDR2. Active high signal. Connect to DDR2 CKE
signal.
DDR2 Chip Select. All commands are masked when DDR2_CS
DDR2_CS
corresponding external bank.
DDR2 Data In/Out. Connect to corresponding DDR2_DATA pins.
DDR2 Input Data Mask. Mask for the DDR2 write data if driven high. Sampled on
both edges of DDR2_DQS at DDR2 side. DM0 corresponds to DDR2_DATA 7–0 and
DM1 corresponds to DDR2_DATA15–8.
Data Strobe. Output with Write Data. Input with Read Data. DQS0 corresponds to
DDR2_DATA 7–0 and DQS1 corresponds to DDR2_DATA 15–8. Based on software
control via the DDR2CTL3 register, this pin can be single-ended or differential.
DDR2 Row Address Strobe. Connect to DDR2_RAS pin; in conjunction with other
DDR2 command pins, defines the operation for the DDR2 to perform.
DDR2 Write Enable. Connect to DDR2_WE pin; in conjunction with other DDR2
command pins, defines the operation for the DDR2 to perform.
DDR2 Memory Clocks. Two differential outputs available via software control
(DDR2CTL0 register). Free running, minimum frequency not guaranteed during reset.
DDR2 On Die Termination. ODT pin when driven high (along with other require-
ments) enables the DDR2 termination resistances. ODT is enabled/disabled
regardless of read or write commands.
9: A = asynchronous, I = input, O = output, S = synchronous, A/D = active drive,
3-0
are decoded memory address lines. Each DDR2_CS
2–0
define which mode registers,
ADSP-21469
3-0
3-0
is driven high.
line selects the