ADSP-21469KBCZ-3 Analog Devices Inc, ADSP-21469KBCZ-3 Datasheet - Page 44

• Manufacturer Part Number: ADSP-21469KBCZ-3
• Description: 400MHz SHARC Processor W/5 Mbits Ram
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: Floating Pointr

Specifications of ADSP-21469KBCZ-3

• Interface: DAI, DPI, EBI/EMI, I²C, SCI, SPI, SSP, UART/USART
• Clock Rate: 400MHz
• Non-volatile Memory: External
• On-chip Ram: 5Mb
• Voltage - I/o: 3.30V
• Voltage - Core: 1.05V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 324-BGA, 324-CSP
• Package: 324CSP-BGA
• Numeric And Arithmetic Format: Floating-Point
• Maximum Speed: 400 MHz
• Ram Size: 640 KB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADSP-21469
Parallel Data Acquisition Port (PDAP)
The timing requirements for the PDAP are provided in
Table
the IDP. For details on the operation of the PDAP, see the
Table 40. Parallel Data Acquisition Port (PDAP)
1
Parameter
Timing Requirements
t
t
t
t
t
t
Switching Characteristics
t
t
Data source pins are AMI_ADDR23–4 or DAI pins. Source pins for serial clock and frame sync are 1) AMI_ADDR3–2 pins, 2) DAI pins.
SPHOLD
HPHOLD
PDSD
PDHD
PDCLKW
PDCLK
PDHLDD
PDSTRB
1
1
40. PDAP is the parallel mode operation of channel 0 of
1
1
PDAP_HOLD Setup Before PDAP_CLK Sample Edge
PDAP_HOLD Hold After PDAP_CLK Sample Edge
PDAP_DAT Setup Before Serial Clock PDAP_CLK Sample Edge
PDAP_DAT Hold After Serial Clock PDAP_CLK Sample Edge
Clock Width
Clock Period
Delay of PDAP Strobe After Last PDAP_CLK Capture Edge for a Word
PDAP Strobe Pulse Width
(PDAP_STROBE)
(PDAP_HOLD)
(PDAP_DATA)
(PDAP_CLK)
DAI_P20–1/
DAI_P20–1
DAI_P20–1
ADDR23–4
DAI_P20–1
Rev. 0 | Page 44 of 72 | June 2010
SAMPLE EDGE
t
PDCLKW
Figure 29. PDAP Timing
t
SPHOLD
t
PDSD
PDAP chapter of the ADSP-214xx SHARC Processor Hardware
Reference. Note that the 20 bits of external PDAP data can be
provided through the AMI_ADDR23–4 pins or over the DAI
pins.
t
t
PDHLDD
HPHOLD
t
t
PDCLK
PDHD
t
PDSTRB
Min
2.5
2.5
3.85
2.5
(t
t
2 × t
2 × t
PCLK
PCLK
× 4
PCLK
PCLK
× 4) ÷ 2 – 3
+ 3
– 1
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns