ADSP-21469KBCZ-3 Analog Devices Inc, ADSP-21469KBCZ-3 Datasheet - Page 15

• Manufacturer Part Number: ADSP-21469KBCZ-3
• Description: 400MHz SHARC Processor W/5 Mbits Ram
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: Floating Pointr

Specifications of ADSP-21469KBCZ-3

• Interface: DAI, DPI, EBI/EMI, I²C, SCI, SPI, SSP, UART/USART
• Clock Rate: 400MHz
• Non-volatile Memory: External
• On-chip Ram: 5Mb
• Voltage - I/o: 3.30V
• Voltage - Core: 1.05V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 324-BGA, 324-CSP
• Package: 324CSP-BGA
• Numeric And Arithmetic Format: Floating-Point
• Maximum Speed: 400 MHz
• Ram Size: 640 KB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 9. Pin Descriptions (Continued)
1
Name
TDI
TDO
TMS
TCK
TRST
EMU
CLK_CFG
CLKIN
XTAL
RESET
RESETOUT/
RUNRSTIN
BOOT_CFG
The following symbols appear in the Type column of
O/D = open-drain, and T = three-state, ipd = internal pull-down resistor, ipu = internal pull-up resistor.
The internal pull-up (ipu) and internal pull-down (ipd) resistors are designed to hold the internal path from the pins at the expected logic levels.
To pull-up or pull-down the external pads to the expected logic levels, use external resistors. Internal pull-up/pull-down resistors cannot be
enabled/disabled and the value of these resistors cannot be programmed. The range of an ipu resistor can be between 26 k–63 k. The range
of an ipd resistor can be between 31 k–85 k.
In this table, the DDR2 pins are SSTL18 compliant. All other pins are LVTTL compliant.
The MLB pins are only available on automotive models of the ADSP-21469 processors. These pins are NC (no connect) on the standard models. For more information, see
CSP_BGA Ball Assignment—Automotive Models on Page
1–0
2–0
Type
I (ipu)
O /T
I (ipu)
I
I (ipu)
O/T (ipu)
I
I
O
I
I/O (ipu)
I
State During/
After Reset
High-Z
High-Z
63, and
Rev. 0 | Page 15 of 72 | June 2010
Table
CSP_BGA Ball Assignment—Standard Models on Page
Description
Test Data Input (JTAG). Provides serial data for the boundary scan logic.
Test Data Output (JTAG). Serial scan output of the boundary scan path.
Test Mode Select (JTAG). Used to control the test state machine.
Test Clock (JTAG). Provides a clock for JTAG boundary scan. TCK must be asserted
(pulsed low) after power-up or held low for proper operation of the device.
Test Reset (JTAG). Resets the test state machine. TRST must be asserted (pulsed low)
after power-up or held low for proper operation of the processor.
Emulation Status. Must be connected to the
product line of JTAG emulators target board connector only.
Core to CLKIN Ratio Control. These pins set the start up clock frequency. Note that
the operating frequency can be changed by programming the PLL multiplier and
divider in the PMCTL register at any time after the core comes out of reset. The
allowed values are:
00 = 6:1
01 = 32:1
10 = 16:1
11 = reserved
Local Clock In. Used in conjunction with XTAL. CLKIN is the clock input. It configures
the processors to use either its internal clock generator or an external clock source.
Connecting the necessary components to CLKIN and XTAL enables the internal clock
generator. Connecting the external clock to CLKIN while leaving XTAL unconnected
configures the processors to use the external clock source such as an external clock
oscillator. CLKIN may not be halted, changed, or operated below the specified
frequency.
Crystal Oscillator Terminal. Used in conjunction with CLKIN to drive an external
crystal.
Processor Reset. Resets the processor to a known state. Upon deassertion, there is
a 4096 CLKIN cycle latency for the PLL to lock. After this time, the core begins program
execution from the hardware reset vector address. The RESET input must be asserted
(low) at power-up.
Reset Out/Running Reset In. The default setting on this pin is reset out. This pin also
has a second function as RUNRSTIN which is enabled by setting bit 0 of the
RUNRSTCTL register. For more information, see the ADSP-214xx SHARC Processor
Hardware Reference.
Boot Configuration Select. These pins select the boot mode for the processor. The
BOOT_CFG pins must be valid before RESET (hardware and software) is de-asserted.
9: A = asynchronous, I = input, O = output, S = synchronous, A/D = active drive,
66.
ADSP-21469
Analog Devices DSP Tools
ADSP-21469