ADSP-21469KBCZ-3 Analog Devices Inc, ADSP-21469KBCZ-3 Datasheet - Page 35

• Manufacturer Part Number: ADSP-21469KBCZ-3
• Description: 400MHz SHARC Processor W/5 Mbits Ram
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: Floating Pointr

Specifications of ADSP-21469KBCZ-3

• Interface: DAI, DPI, EBI/EMI, I²C, SCI, SPI, SSP, UART/USART
• Clock Rate: 400MHz
• Non-volatile Memory: External
• On-chip Ram: 5Mb
• Voltage - I/o: 3.30V
• Voltage - Core: 1.05V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 324-BGA, 324-CSP
• Package: 324CSP-BGA
• Numeric And Arithmetic Format: Floating-Point
• Maximum Speed: 400 MHz
• Ram Size: 640 KB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AMI Write
Use these specifications for asynchronous interfacing to memo-
ries. Note that timing for AMI_ACK, AMI_DATA, AMI_RD,
AMI_WR, and strobe timing parameters only apply to asyn-
chronous access mode.
Table 31. Memory Write
1
2
3
4
5
Parameter
Timing Requirements
t
t
Switching Characteristics
t
t
t
t
t
t
t
t
t
t
W = (number of wait states specified in AMICTLx register) × t
AMI_ACK delay/setup: System must meet t
The falling edge of AMI_MSx is referenced.
Note that timing for AMI_ACK, AMI_DATA, AMI_RD, AMI_WR, and strobe timing parameters only applies to asynchronous access mode.
See
For Write to Write: t
DAAK
DSAK
DAWH
DAWL
WW
DDWH
DWHA
DWHD
DATRWH
WWR
DDWR
WDE
Test Conditions on Page 58
AMI_ADDR
AMI_DATA
AMI_ACK
DDR2_CLK
AMI_ACK Delay from Address, Selects
AMI_ACK Delay from AMI_WR Low
Address, Selects to AMI_WR Deasserted
Address, Selects to AMI_WR Low
AMI_WR Pulse Width
Data Setup Before AMI_WR High
Address Hold After AMI_WR Deasserted
Data Hold After AMI_WR Deasserted
Data Disable After AMI_WR Deasserted
AMI_WR High to AMI_WR Low
Data Disable Before AMI_RD Low
AMI_WR Low to Data Enabled
+ H, for both same bank and different bank. For Write to Read: (3 × t
for calculation of hold times given capacitive and dc loads.
t
DAWL
DAAK
t
WDE
, or t
t
DAAK
DSAK
, for deassertion of AMI_ACK (low).
t
5
DSAK
2
Rev. 0 | Page 35 of 72 | June 2010
1, 3
1, 2
4
2
Figure 21. AMI Write
SDDR
t
DAWH
2_
CLK
Min
t
t
W – 1.3
t
H + 0.15
H
t
t
2t
t
DDR
DDR
DDR
DDR
DDR
DDR
t
DDWH
DDR
H = (number of hold cycles specified in AMICTLx register) × t
2_
2_
2_
2_
2_
2_
2_
t
CLK
CLK
CLK
CLK
CLK
CLK
WW
CLK
– 3.1+ W
– 3
– 3.0+ W
– 1.5+ H
– 3.5
– 1.37 + H
– 6
DDR2_CLK
) + H, for the same bank and different banks.
Max
t
W – 6
t
DDR
DDR
2_
2_
t
DATRWH
CLK
CLK
– 9.7 + W
+ 4.9 + H
t
DWHD
t
WWR
t
DWHA
t
DDWR
ADSP-21469
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
DDR
2_
CLK