DS72030W200FPV Renesas Electronics America, DS72030W200FPV Datasheet - Page 996

• Manufacturer Part Number: DS72030W200FPV
• Description: MPU, 32BIT, SH7203, ROMLESS, 240QFP
• Manufacturer: Renesas Electronics America
• Series: SH7200r

Specifications of DS72030W200FPV

• Core Size: 32bit
• Program Memory Size: 32KB
• Cpu Speed: 200MHz
• Digital Ic Case Style: QFP
• No. Of Pins: 240
• Supply Voltage Range: 1.1V To 1.3V
• Operating Temperature Range: -20°C To +85°C
• Svhc: No SVHC
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Section 19 Controller Area Network (RCAN-TL1)
(2)
The TXCR1 and TXCR0 are 16-bit read/conditionally-write registers. The TXCR1 controls
Mailbox-31 to Mailbox-16, and the TXCR0 controls Mailbox-15 to Mailbox-1.This register is
used by the CPU to request the pending transmission requests in the TXPR to be cancelled. To
clear the corresponding bit in the TXPR the CPU must write a ‘1’ to the bit position in the TXCR.
Writing a ‘0’ has no effect.
When an abort has succeeded the CAN controller clears the corresponding TXPR + TXCR bits,
and sets the corresponding ABACK bit. However, once a Mailbox has started a transmission, it
cannot be cancelled by this bit. In such a case, if the transmission finishes in success, the CAN
controller clears the corresponding TXPR + TXCR bit, and sets the corresponding TXACK bit,
however, if the transmission fails due to a bus arbitration loss or an error on the bus, the CAN
controller clears the corresponding TXPR + TXCR bit, and sets the corresponding ABACK bit. If
an attempt is made by the CPU to clear a mailbox transmission that is not transmit-pending it has
no effect. In this case the CPU will be not able at all to set the TXCR flag.
• TXCR1
Note: * Only writing a ‘1’ to a Mailbox that is requested for transmission and is configured as
Bits 15 to 0 — Requests the corresponding Mailbox, that is in the queue for transmission, to
cancel its transmission. The bit 15 to 0 corresponds to Mailbox-31 to 16 (and TXPR1[15:0])
respectively.
Rev. 3.00 Sep. 28, 2009 Page 964 of 1650
REJ09B0313-0300
Bit[15:0]:TXCR1
0
1
Initial value:
Transmit Cancel Register (TXCR1, TXCR0)
R/W:
Bit:
transmit.
R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W*
15
0
14
0
Description
Transmit message cancellation idle state in corresponding mailbox (Initial
value)
[Clearing Condition]
Completion of transmit message cancellation (automatically cleared)
Transmission cancellation request made for corresponding mailbox
13
0
12
0
11
0
10
0
9
0
TXCR1[15:0]
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0