DS72030W200FPV Renesas Electronics America, DS72030W200FPV Datasheet - Page 860
DS72030W200FPV
Manufacturer Part Number
DS72030W200FPV
Description
MPU, 32BIT, SH7203, ROMLESS, 240QFP
Manufacturer
Renesas Electronics America
Series
SH7200r
Datasheet
1.R5S72030W200FP.pdf
(1686 pages)
Specifications of DS72030W200FPV
Core Size
32bit
Program Memory Size
32KB
Cpu Speed
200MHz
Digital Ic Case Style
QFP
No. Of Pins
240
Supply Voltage Range
1.1V To 1.3V
Operating Temperature Range
-20°C To +85°C
Svhc
No SVHC
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- Current page: 860 of 1686
- Download datasheet (10Mb)
Section 16 Synchronous Serial Communication Unit (SSU)
(4)
Data Transmission/Reception
Figure 16.17 shows a flowchart example of simultaneous transmission/reception. The data
transmission/reception is performed combining the data transmission and data reception as
mentioned above. The data transmission/reception is started by writing transmit data to SSTDR
with TE = RE = 1. When the RDRF bit is set to 1, at the 8th rising edge of the transfer clock the
ORER bit in SSSR is set to 1, an overrun error (SSERI) is generated, and both transmission and
reception are stopped. Transmission and reception are not possible while the ORER bit is set to 1.
To resume transmission and reception, clear the ORER bit to 0.
Before switching transmission mode (TE = 1) or reception mode (RE = 1) to
transmission/reception mode (TE = RE = 1), clear the TE and RE bits to 0. When starting the
transfer, confirm that the TEND, RDRF, and ORER bits are cleared to 0 before setting the TE or
RE bits to 1.
Rev. 3.00 Sep. 28, 2009 Page 828 of 1650
REJ09B0313-0300
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