DS72030W200FPV Renesas Electronics America, DS72030W200FPV Datasheet - Page 1243

• Manufacturer Part Number: DS72030W200FPV
• Description: MPU, 32BIT, SH7203, ROMLESS, 240QFP
• Manufacturer: Renesas Electronics America
• Series: SH7200r

Specifications of DS72030W200FPV

• Core Size: 32bit
• Program Memory Size: 32KB
• Cpu Speed: 200MHz
• Digital Ic Case Style: QFP
• No. Of Pins: 240
• Supply Voltage Range: 1.1V To 1.3V
• Operating Temperature Range: -20°C To +85°C
• Svhc: No SVHC
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 23.22 Timing at which BRDY Interrupts are Generated
Note: This function is valid only in the reading direction of reading from the buffer memory. In the
(4)
(a)
Figure 23.15 shows a diagram of the timing up to the point where the FRDY and DTLN bits are
determined when the pipe specified by the FIFO port has been switched (the CURPIPE bit in
C/DnFIFOSEL has been changed).
If the CURPIPE bits have been changed, access to the FIFO port should be carried out after
waiting 450 ns and 8 clock cycles at a peripheral clock after writing to C/DnFIFOSEL.
The same timing applies with respect to the CFIFO port, when the ISEL bit is changed.
Buffer State
When Packet is Received
Buffer full (normal packet received)
Zero-length packet received
Normal short packet received
Transaction count ended
Timing at which the FIFO Port can be Accessed
Timing at which the FIFO Port can be Accessed when Switching Pipes
writing direction, the BFRE bit should be fixed at 0.
Register setting
BFRE = 0
When packet is received
When packet is received
When packet is received
When packet is received
Section 23 USB 2.0 Host/Function Module (USB)
Rev. 3.00 Sep. 28, 2009 Page 1211 of 1650
BFRE = 1
Not generated
When packet is received
When reading of the received
data from the buffer memory
has been completed
When reading of the received
data from the buffer memory
has been completed
REJ09B0313-0300