DS72030W200FPV Renesas Electronics America, DS72030W200FPV Datasheet - Page 240
DS72030W200FPV
Manufacturer Part Number
DS72030W200FPV
Description
MPU, 32BIT, SH7203, ROMLESS, 240QFP
Manufacturer
Renesas Electronics America
Series
SH7200r
Datasheet
1.R5S72030W200FP.pdf
(1686 pages)
Specifications of DS72030W200FPV
Core Size
32bit
Program Memory Size
32KB
Cpu Speed
200MHz
Digital Ic Case Style
QFP
No. Of Pins
240
Supply Voltage Range
1.1V To 1.3V
Operating Temperature Range
-20°C To +85°C
Svhc
No SVHC
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- Current page: 240 of 1686
- Download datasheet (10Mb)
Section 7 User Break Controller (UBC)
Rev. 3.00 Sep. 28, 2009 Page 208 of 1650
REJ09B0313-0300
Bit
19
18
17, 16
15
14
Bit Name
UTOD1
UTOD0
CKS[1:0]
SCMFC0
SCMFC1
Initial
Value
0
0
00
0
0
R/W
R/W
R/W
R/W
R/W
R/W
Description
UBCTRG Output Disable 1
Specifies whether a trigger signal is output to the
UBCTRG pin when a break condition for channel 1 is
satisfied.
0: Outputs a trigger signal to the UBCTRG pin when a
1: Does not output a trigger signal to the UBCTRG pin
UBCTRG Output Disable 0
Specifies whether a trigger signal is output to the
UBCTRG pin when a break condition for channel 0 is
satisfied.
0: Outputs a trigger signal to the UBCTRG pin when a
1: Does not output a trigger signal to the UBCTRG pin
Clock Select
Specifies the pulse width output to the UBCTRG pin
when a break condition is satisfied.
00: Pulse width of UBCTRG is one bus clock cycle
01: Pulse width of UBCTRG is two bus clock cycles
10: Pulse width of UBCTRG is four bus clock cycles
11: Pulse width of UBCTRG is eight bus clock cycles
C Bus Cycle Condition Match Flag 0
When the C bus cycle condition in the break conditions
set for channel 0 is satisfied, this flag is set to 1. In
order to clear this flag, write 0 to this bit.
0: The C bus cycle condition for channel 0 does not
1: The C bus cycle condition for channel 0 matches
C Bus Cycle Condition Match Flag 1
When the C bus cycle condition in the break conditions
set for channel 1 is satisfied, this flag is set to 1. In
order to clear this flag, write 0 to this bit.
0: The C bus cycle condition for channel 1 does not
1: The C bus cycle condition for channel 1 matches
match
break condition for channel 1 is satisfied
when a break condition for channel 1 is satisfied
break condition for channel 0 is satisfied
match
when a break condition for channel 0 is satisfied
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