DS72030W200FPV Renesas Electronics America, DS72030W200FPV Datasheet - Page 477
DS72030W200FPV
Manufacturer Part Number
DS72030W200FPV
Description
MPU, 32BIT, SH7203, ROMLESS, 240QFP
Manufacturer
Renesas Electronics America
Series
SH7200r
Datasheet
1.R5S72030W200FP.pdf
(1686 pages)
Specifications of DS72030W200FPV
Core Size
32bit
Program Memory Size
32KB
Cpu Speed
200MHz
Digital Ic Case Style
QFP
No. Of Pins
240
Supply Voltage Range
1.1V To 1.3V
Operating Temperature Range
-20°C To +85°C
Svhc
No SVHC
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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10.5.3
In case that one or more channels are set that transfer request source is external request signal
DREQ, please use one of the following four ways.
1) Please set all channels to cycle-steal mode.
2) Please set all channels to burst-mode with all of the following three conditions.
3) If there are both of one or more channels set to cycle-steal mode and one or more channels set
4) Please use only one channel.
If using other than the above four ways, there is a possibility that DACKn pin and TENDn pin
show wrong transfer channel and since then until power-on reset DMA transfer is unavailable.
Additionally if this state occurs in burst-mode, CPU becomes unable to fetch instructions, then
system becomes suspended.
2-1) Please set channel priority mode to fixed mode 1 or fixed mode 2.
2-2) Please set all channels to dual-address mode.
2-3) Please set transfer source address and transfer destination address of each channels to one
to burst mode, please use with all of the following three conditions.
3-1) Please set channel priority mode to fixed mode 1 or fixed mode 2.
3-2) Please set all channels to dual-address mode.
3-3) Please set transfer source address and transfer destination address of each channels to one
A. transfer source address:
B. transfer source address:
C. transfer source address:
A. transfer source address:
B. transfer source address:
C. transfer source address:
of the followings.
of the followings.
Notice about using external request mode
transfer destination address: external address space
transfer destination address: internal address space
transfer destination address: internal address space
transfer destination address: external address space
transfer destination address: internal address space
transfer destination address: internal address space
external address space
external address space
internal address space
external address space
external address space
internal address space
Section 10 Direct Memory Access Controller (DMAC)
Rev. 3.00 Sep. 28, 2009 Page 445 of 1650
REJ09B0313-0300
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