DS72030W200FPV Renesas Electronics America, DS72030W200FPV Datasheet - Page 1279

• Manufacturer Part Number: DS72030W200FPV
• Description: MPU, 32BIT, SH7203, ROMLESS, 240QFP
• Manufacturer: Renesas Electronics America
• Series: SH7200r

Specifications of DS72030W200FPV

• Core Size: 32bit
• Program Memory Size: 32KB
• Cpu Speed: 200MHz
• Digital Ic Case Style: QFP
• No. Of Pins: 240
• Supply Voltage Range: 1.1V To 1.3V
• Operating Temperature Range: -20°C To +85°C
• Svhc: No SVHC
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

24.3.6
When a DSTN panel is used, LDSARL specifies the fetch start address for the lower side of the
panel. The register setting is updated with the Vsync timing when the LCDC is active.
Initial value:
Initial value:
Bit
31 to 28
27, 26
25 to 4
3 to 0
R/W:
R/W:
Bit:
Bit:
SAL15 SAL14 SAL13 SAL12 SAL11 SAL10
R/W
LCDC Start Address Register for Lower Display Data Fetch (LDSARL)
31
15
R
0
0
-
Bit Name
⎯
⎯
SAL25 to
SAL4
⎯
R/W
30
14
R
0
0
-
R/W
29
13
R
0
0
-
Initial
Value
All 0
All 1
All 0
All 0
R/W
28
12
R
0
0
-
R/W
27
11
R
1
0
-
R/W
R
R
R/W
R
R/W
26
10
R
1
0
-
SAL25 SAL24 SAL23 SAL22 SAL21 SAL20 SAL19 SAL18 SAL17 SAL16
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Reserved
These bits are always read as 1. The write value should
always be 1.
Start Address for Lower Panel Display Data Fetch
The start address for data fetch of the display data must
be set within the synchronous DRAM area of area 3.
STN and TFT: Cannot be used
DSTN: Start address for fetching display data
Reserved
These bits are always read as 0. The write value should
always be 0.
SAL9
R/W
R/W
25
0
9
0
SAL8
R/W
R/W
24
0
8
0
corresponding to the lower panel
SAL7
R/W
R/W
23
0
7
0
Rev. 3.00 Sep. 28, 2009 Page 1247 of 1650
SAL6
R/W
R/W
22
0
6
0
R/W
SAL5
R/W
21
Section 24 LCD Controller (LCDC)
0
5
0
R/W
SAL4
R/W
20
0
4
0
R/W
19
R
0
3
0
-
REJ09B0313-0300
R/W
18
R
0
2
0
-
R/W
17
R
0
1
0
-
R/W
16
R
0
0
0
-