DS72030W200FPV Renesas Electronics America, DS72030W200FPV Datasheet - Page 270

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DS72030W200FPV

Manufacturer Part Number
DS72030W200FPV
Description
MPU, 32BIT, SH7203, ROMLESS, 240QFP
Manufacturer
Renesas Electronics America
Series
SH7200r
Datasheet

Specifications of DS72030W200FPV

Core Size
32bit
Program Memory Size
32KB
Cpu Speed
200MHz
Digital Ic Case Style
QFP
No. Of Pins
240
Supply Voltage Range
1.1V To 1.3V
Operating Temperature Range
-20°C To +85°C
Svhc
No SVHC
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Section 8 Cache
8.4.4
1. Programs that access memory-mapped cache of the operand cache should be placed in a cache-
2. Rewriting the address array contents so that two or more ways are hit simultaneously is
3. Registers and memory-mapped cache can be accessed only by the CPU and not by the DMAC.
Rev. 3.00 Sep. 28, 2009 Page 238 of 1650
REJ09B0313-0300
disabled space. Programs that access memory-mapped cache of the instruction cache should be
placed in a cache-disabled space, and in each of the beginning and the end of that, two or more
read accesses to on-chip peripheral modules or external address space (cache-disabled address)
should be executed.
prohibited. Operation is not guaranteed if the address array contents are changed so that two or
more ways are hit simultaneously.
Notes

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