DS72030W200FPV Renesas Electronics America, DS72030W200FPV Datasheet - Page 528

• Manufacturer Part Number: DS72030W200FPV
• Description: MPU, 32BIT, SH7203, ROMLESS, 240QFP
• Manufacturer: Renesas Electronics America
• Series: SH7200r

Specifications of DS72030W200FPV

• Core Size: 32bit
• Program Memory Size: 32KB
• Cpu Speed: 200MHz
• Digital Ic Case Style: QFP
• No. Of Pins: 240
• Supply Voltage Range: 1.1V To 1.3V
• Operating Temperature Range: -20°C To +85°C
• Svhc: No SVHC
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
Notes: 1. TADCR must not be accessed in eight bits; it should always be accessed in 16 bits.
Table 11.27 Setting of Transfer Timing by Bits BF1 and BF0
Notes: 1. Data is transferred from the cycle set buffer register to the cycle set register when the
Rev. 3.00 Sep. 28, 2009 Page 496 of 1650
REJ09B0313-0300
Bit
0
Bit 7
BF1
0
0
1
1
2. When interrupt skipping is disabled (the T3AEN and T4VEN bits in the timer interrupt
3. If link with interrupt skipping is enabled while interrupt skipping is disabled, A/D
* Do not set to 1 when complementary PWM mode is not selected.
2. These settings are prohibited when complementary PWM mode is not selected.
Bit Name
ITB4VE
skipping set register (TITCR) are cleared to 0 or the skipping count set bits (3ACOR
and 4VCOR) in TITCR are cleared to 0), do not link A/D converter start requests with
interrupt skipping operation (clear the ITA3AE, ITA4VE, ITB3AE, and ITB4VE bits in the
timer A/D converter start request control register (TADCR) to 0).
converter start requests will not be issued.
crest of the TCNT_4 count is reached in complementary PWM mode, when compare
match occurs between TCNT_3 and TGRA_3 in reset-synchronized PWM mode, or
when compare match occurs between TCNT_4 and TGRA_4 in PWM mode 1 or
normal operation mode.
Bit 6
BF0
0
1
0
1
Initial
Value
0*
Description
Does not transfer data from the cycle set buffer register to the cycle
set register.
Transfers data from the cycle set buffer register to the cycle set
register at the crest of the TCNT_4 count.*
Transfers data from the cycle set buffer register to the cycle set
register at the trough of the TCNT_4 count.*
Transfers data from the cycle set buffer register to the cycle set
register at the crest and trough of the TCNT_4 count.*
R/W
R/W
Description
TCIV_4 Interrupt Skipping Link Enable
Select whether to link A/D converter start requests
(TRG4BN) with TCIV_4 interrupt skipping operation.
0: Does not link with TCIV_4 interrupt skipping
1: Links with TCIV_4 interrupt skipping
1
2
2