DS72030W200FPV Renesas Electronics America, DS72030W200FPV Datasheet - Page 1113
DS72030W200FPV
Manufacturer Part Number
DS72030W200FPV
Description
MPU, 32BIT, SH7203, ROMLESS, 240QFP
Manufacturer
Renesas Electronics America
Series
SH7200r
Datasheet
1.R5S72030W200FP.pdf
(1686 pages)
Specifications of DS72030W200FPV
Core Size
32bit
Program Memory Size
32KB
Cpu Speed
200MHz
Digital Ic Case Style
QFP
No. Of Pins
240
Supply Voltage Range
1.1V To 1.3V
Operating Temperature Range
-20°C To +85°C
Svhc
No SVHC
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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22.3.13 Transfer Control Register (FLTRCR)
Setting the TRSTRT bit to 1 initiates access to flash memory. Access completion can be checked
by the TREND bit. During the transfer (from when the TRSTRT bit is set to 1 until the TREND
bit is set to 1), the processing should not be forcibly ended (by setting the TRSTRT bit to 0).
When reading from flash memory, TREND is set when reading from flash memory have been
finished. However, if there is any read data remaining in the FIFO, the processing should not be
forcibly ended until all data has been read from the FIFO.
Bit
7 to 2
1
0
Bit Name
—
TREND
TRSTRT
Initial value:
Initial
Value
All 0
0
0
R/W:
Bit:
R/W
R
R/W
R/W
R
7
0
-
R
6
0
-
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Processing End Flag Bit
Indicates that the processing performed in the specified
access mode has been completed. The write value
should always be 0.
Transfer Start
By setting this bit from 0 to 1 when the TREND bit is 0,
processing in the access mode specified by the access
mode specification bits ACM[1:0] is initiated.
0: Stops transfer
1: Starts transfer
R
5
0
-
Section 22 AND/NAND Flash Memory Controller (FLCTL)
R
4
0
-
R
3
0
-
Rev. 3.00 Sep. 28, 2009 Page 1081 of 1650
R
2
0
-
END
R/W
TR
1
0
STRT
R/W
TR
0
0
REJ09B0313-0300
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