MCIMX53-START Freescale Semiconductor, MCIMX53-START Datasheet - Page 90

• Manufacturer Part Number: MCIMX53-START
• Description: KIT DEVELOPMENT I.MX53
• Manufacturer: Freescale Semiconductor
• Series: i.MX53r
• Type: MCUr

Specifications of MCIMX53-START

• Contents: Board
• Silicon Manufacturer: Freescale
• Core Architecture: ARM
• Core Sub-architecture: Cortex - A8
• Silicon Core Number: I.MX5
• Silicon Family Name: I.MX53
• Peak Reflow Compatible (260 C): Yes
• Rohs Compliant: Yes
• Leaded Process Compatible: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: i.MX53
• Lead Free Status / Rohs Status: Supplier Unconfirmed

Electrical Characteristics
The maximal accuracy of UP/DOWN edge of controls is:
90
1
2
IP5o
IP13o Offset of VSYNC
IP8o
IP9o
Display interface clock period immediate value.
DISP_CLK_PERIOD—number of DI_CLK per one Tdicp. Resolution 1/16 of DI_CLK.
DI_CLK_PERIOD—relation of between programing clock frequency and current system clock frequency
Display interface clock period average value.
DI’s counter can define offset, period and UP/DOWN characteristic of output signal according to programed parameters of the
counter. Same of parameters in the table are not defined by DI’s registers directly (by name), but can be generated by
corresponding DI’s counter. The SCREEN_WIDTH is an input value for DI’s HSYNC generation counter. The distance
between HSYNCs is a SCREEN_WIDTH.
ID
Offset of IPP_DISP_CLK
Offset of HSYNC
Offset of DRDY
Table 57. Synchronous Display Interface Timing Characteristics (Pixel Level) (continued)
Tdicp
Parameter
=
⎧
⎪
⎪
⎨
⎪
⎪
⎩
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1
T diclk floor
T diclk
⎛
⎝
×
DISP_CLK_PERIOD
--------------------------------------------------- -
DI_CLK_PERIOD
Symbol
DISP_CLK_PERIOD
--------------------------------------------------- -
Todrdy
Todicp
DI_CLK_PERIOD
Tovs
Tohs
Tdicp
Accuracy
=
DISP_CLK_OFFSET
T diclk
VSYNC_OFFSET
HSYNC_OFFSET
DRDY_OFFSET
=
,
×
×
×
×
×
(
Value
0.5 T diclk
Tdiclk
Tdiclk
Tdiclk
Tdiclk
DISP_CLK_PERIOD
--------------------------------------------------- -
+
DI_CLK_PERIOD
0.5 0.5
×
±
⎞
⎠
) 0.62ns
,
±
for fractional DISP_CLK_PERIOD
DISP_CLK_OFFSET—offset of
IPP_DISP_CLK edges from local start
point, in DI_CLK
(0.5 DI_CLK Resolution)
Defined by DISP_CLK counter
VSYNC_OFFSET—offset of Vsync edges
from a local start point, when a Vsync
should be active, in DI_CLK
(0.5 DI_CLK Resolution).The
VSYNC_OFFSET should be built by
suitable DI’s counter.
HSYNC_OFFSET—offset of Hsync edges
from a local start point, when a Hsync
should be active, in DI_CLK
(0.5 DI_CLK Resolution).The
HSYNC_OFFSET should be built by
suitable DI’s counter.
DRDY_OFFSET—offset of DRDY edges
from a suitable local start point, when a
corresponding data has been set on the
bus, in DI_CLK
(0.5 DI_CLK Resolution)
The DRDY_OFFSET should be built by
suitable DI’s counter.
for integer DISP_CLK_PERIOD
--------------------------------------------------- -
DI_CLK_PERIOD
--------------------------------------------------- -
DI_CLK_PERIOD
Description
×
×
2
2
Freescale Semiconductor
×
×
2
2
Unit
ns
ns
ns
ns