MCIMX53-START Freescale Semiconductor, MCIMX53-START Datasheet - Page 55

• Manufacturer Part Number: MCIMX53-START
• Description: KIT DEVELOPMENT I.MX53
• Manufacturer: Freescale Semiconductor
• Series: i.MX53r
• Type: MCUr

Specifications of MCIMX53-START

• Contents: Board
• Silicon Manufacturer: Freescale
• Core Architecture: ARM
• Core Sub-architecture: Cortex - A8
• Silicon Core Number: I.MX5
• Silicon Family Name: I.MX53
• Peak Reflow Compatible (260 C): Yes
• Rohs Compliant: Yes
• Leaded Process Compatible: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: i.MX53
• Lead Free Status / Rohs Status: Supplier Unconfirmed

4.6.6.4
Figure 18
timing parameters mentioned previously for specific control parameters settings.
Freescale Semiconductor
1
2
3
t is the maximal EIM logic (axi_clk) cycle time. The maximum allowed axi_clk frequency is 133 MHz, whereas the maximum
allowed BCLK frequency is 104 MHz. As a result, if BCD = 0, axi_clk must be
allowed for axi_clk, resulting in a BCLK of 66.5 MHz. When the clock branch to EIM is decreased to 104 MHz, other busses
are impacted which are clocked from this source. See the CCM chapter of the i.MX53 Reference Manual for a detailed clock
tree description.
BCLK parameters are being measured from the 50% point, that is, high is defined as 50% of signal value and low is defined
as 50% as signal value.
For signal measurements “High” is defined as 80% of signal value and “Low” is defined as 20% of signal value.
ADV_B
CSx_B
BEy_B
ADDR
WE_B
OE_B
DATA
BCLK
to
Examples of EIM Synchronous Accesses
Figure 21
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1
Last Valid Address
provide few examples of basic EIM accesses to external memory devices with the
Figure 18. Synchronous Memory Read Access, WSC=1
WE14
WE10
WE12
WE4
WE6
WE18
WE15
Address v1
≤
104 MHz. If BCD = 1, then 133 MHz is
D(v1)
Electrical Characteristics
WE11
WE7
WE13
WE19
WE5
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