MCIMX53-START Freescale Semiconductor, MCIMX53-START Datasheet - Page 111

KIT DEVELOPMENT I.MX53

MCIMX53-START

Manufacturer Part Number
MCIMX53-START
Description
KIT DEVELOPMENT I.MX53
Manufacturer
Freescale Semiconductor
Series
i.MX53r
Type
MCUr
Datasheets

Specifications of MCIMX53-START

Contents
Board
Silicon Manufacturer
Freescale
Core Architecture
ARM
Core Sub-architecture
Cortex - A8
Silicon Core Number
I.MX5
Silicon Family Name
I.MX53
Peak Reflow Compatible (260 C)
Yes
Rohs Compliant
Yes
Leaded Process Compatible
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
i.MX53
Lead Free Status / Rohs Status
Supplier Unconfirmed

Available stocks

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Part Number
Manufacturer
Quantity
Price
Part Number:
MCIMX53-START
Manufacturer:
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MCIMX53-START-R
Manufacturer:
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Ground = 0.0 V; Load Capacitance = 60 pF; MediaLB speed = 256/512 Fs; Fs = 48 kHz; all timing
parameters specified from the valid voltage threshold as listed below; unless otherwise noted.
1
2
3
Ground = 0.0 V; load capacitance = 40 pF; MediaLB speed = 1024 Fs; Fs = 48 kHz; all timing parameters
specified from the valid voltage threshold as listed in
Freescale Semiconductor
MLBCLK operating frequency
MLBCLK rise time
MLB fall time
MLBCLK cycle time
MLBCLK low time
MLBCLK high time
MLBCLK pulse width variation
MLBSIG/MLBDAT input valid to
MLBCLK falling
MLBSIG/MLBDAT input hold
from MLBCLK low
MLBSIG/MLBDAT output high
impedance from MLBCLK low
Bus Hold Time
The MLB controller can shut off MLBCLK to place MediaLB in a low-power state.
Pulse width variation is measured at 1.25 V by triggering on one edge of MLBCLK and measuring the spread on the other
edge, measured in ns peak-to-peak (pp)
The board must be designed to insure that the high-impedance bus does not leave the logic state of the final driven bit for this
time period. Therefore, coupling must be minimized while meeting the maximum capacitive load listed.
Parameter
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1
1
Symbol
t
t
t
t
t
t
t
Table 63. MLB 256/512 Fs Timing Parameters
t
t
t
dhmcf
mpwv
dsmcf
mcfdz
f
mckh
mdzh
mckc
mckr
mckf
mckl
mck
11.264
31.5
14.5
31.5
14.5
Min
30
14
30
14
1
0
0
4
12.288
24.576
35.5
16.5
36.5
16.5
Typ
81
40
37
17
38
17
Table
64; unless otherwise noted.
24.6272
25.600
Max
t
mckl
3
3
2
Units
ns pp
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Min: 256*fs at 44.0 kHz
Typ: 256*fs at 48.0 kHz
Typ: 512*fs at 48.0 kHz
Max: 512*fs at 48.1 kHz
Max: 512*fs PLL unlocked
Electrical Characteristics
256*Fs PLL unlocked
512*Fs PLL unlocked
256*Fs PLL unlocked
512*Fs PLL unlocked
V
V
Comment
IL
IH
256*Fs
512*Fs
256*Fs
512*Fs
256*Fs
512*Fs
Note
Note
TO V
TO V
2
3
IH
IL
111

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